33 lines
821 B
Verilog
33 lines
821 B
Verilog
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`include "VX_define.v"
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module byte_enabled_simple_dual_port_ram
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(
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input we, clk,
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input wire[4:0] waddr, raddr,
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input wire[`NT_M1:0] be,
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input wire[`NT_M1:0][31:0] wdata,
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output reg[`NT_M1:0][31:0] q
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);
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// Thread Byte Bit
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logic [`NT_M1:0][3:0][7:0] GPR[31:0];
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always_ff@(posedge clk) begin
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if(we) begin
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integer thread_ind;
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for (thread_ind = 0; thread_ind <= `NT_M1; thread_ind = thread_ind + 1) begin
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if(be[thread_ind]) GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
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if(be[thread_ind]) GPR[waddr][thread_ind][1] <= wdata[thread_ind][15:8];
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if(be[thread_ind]) GPR[waddr][thread_ind][2] <= wdata[thread_ind][23:16];
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if(be[thread_ind]) GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
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end
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end
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end
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always_ff@(negedge clk) begin
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q <= GPR[raddr];
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end
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endmodule |