d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
54 lines
1.3 KiB
Systemverilog
54 lines
1.3 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_elastic_adapter (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire ready_out,
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output wire valid_out,
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input wire busy,
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output wire strobe
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);
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wire push = valid_in && ready_in;
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wire pop = valid_out && ready_out;
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reg loaded;
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always @(posedge clk) begin
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if (reset) begin
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loaded <= 0;
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end else begin
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if (push) begin
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loaded <= 1;
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end
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if (pop) begin
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loaded <= 0;
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end
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end
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end
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assign ready_in = ~loaded;
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assign valid_out = loaded && ~busy;
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assign strobe = push;
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endmodule
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`TRACING_ON
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