61 lines
1.4 KiB
Verilog
61 lines
1.4 KiB
Verilog
`include "VX_define.vh"
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// control module to support multi-cycle read for fp register
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module VX_gpr_fp_ctrl (
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input wire clk,
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input wire reset,
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input wire [`NUM_THREADS-1:0][31:0] rs1_data,
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input wire [`NUM_THREADS-1:0][31:0] rs2_data,
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// outputs
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output wire [`NW_BITS+`NR_BITS-1:0] raddr1,
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VX_gpr_read_if gpr_read_if
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);
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reg [`NUM_THREADS-1:0][31:0] rs1_tmp_data, rs2_tmp_data, rs3_tmp_data;
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reg read_rs1;
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reg [`NW_BITS-1:0] rs3_wid;
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wire rs3_delay = gpr_read_if.valid && gpr_read_if.use_rs3 && read_rs1;
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wire read_fire = gpr_read_if.valid && gpr_read_if.ready_out;
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always @(posedge clk) begin
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if (reset) begin
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rs1_tmp_data <= 0;
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rs2_tmp_data <= 0;
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rs3_tmp_data <= 0;
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read_rs1 <= 1;
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rs3_wid <= 0;
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end else begin
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if (rs3_delay) begin
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read_rs1 <= 0;
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rs3_wid <= gpr_read_if.wid;
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end else if (read_fire) begin
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read_rs1 <= 1;
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end
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if (read_rs1) begin
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rs1_tmp_data <= rs1_data;
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end
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rs2_tmp_data <= rs2_data;
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rs3_tmp_data <= rs1_data;
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assert(read_rs1 || rs3_wid == gpr_read_if.wid);
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end
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end
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always @(posedge clk) begin
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end
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// outputs
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wire [`NR_BITS-1:0] rs1 = read_rs1 ? gpr_read_if.rs1 : gpr_read_if.rs3;
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assign raddr1 = {gpr_read_if.wid, rs1};
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assign gpr_read_if.ready_in = ~rs3_delay;
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assign gpr_read_if.rs1_data = rs1_tmp_data;
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assign gpr_read_if.rs2_data = rs2_tmp_data;
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assign gpr_read_if.rs3_data = rs3_tmp_data;
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endmodule |