23 lines
650 B
Verilog
23 lines
650 B
Verilog
`ifndef VX_LSU_REQ_IF
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`define VX_LSU_REQ_IF
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`include "VX_define.vh"
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interface VX_lsu_req_if ();
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wire valid;
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wire [`NW_BITS-1:0] wid;
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wire [`NUM_THREADS-1:0] tmask;
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wire [31:0] PC;
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wire rw;
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wire [`BYTEEN_BITS-1:0] byteen;
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wire [`NUM_THREADS-1:0][31:0] store_data;
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wire [`NUM_THREADS-1:0][31:0] base_addr;
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wire [31:0] offset;
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wire [`NR_BITS-1:0] rd;
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wire wb;
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wire ready;
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endinterface
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`endif |