14 lines
173 B
Verilog
14 lines
173 B
Verilog
`include "../VX_define.v"
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`ifndef VX_GPR_JAL_INTER
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`define VX_GPR_JAL_INTER
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interface VX_gpr_jal_inter ();
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wire is_jal;
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wire[31:0] curr_PC;
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endinterface
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`endif |