69 lines
1.7 KiB
Verilog
69 lines
1.7 KiB
Verilog
`include "VX_platform.vh"
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module VX_ipdom_stack #(
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parameter WIDTH = 1,
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parameter DEPTH = 1
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) (
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input wire clk,
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input wire reset,
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input wire [WIDTH - 1:0] q1,
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input wire [WIDTH - 1:0] q2,
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output wire [WIDTH - 1:0] d,
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input wire push,
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input wire pop,
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output wire empty,
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output wire full
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);
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localparam ADDRW = $clog2(DEPTH);
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reg is_part [DEPTH-1:0];
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reg [ADDRW-1:0] rd_ptr, wr_ptr;
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wire [WIDTH-1:0] d1, d2;
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always @(posedge clk) begin
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if (reset) begin
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rd_ptr <= 0;
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wr_ptr <= 0;
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end else begin
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if (push) begin
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rd_ptr <= wr_ptr;
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wr_ptr <= wr_ptr + ADDRW'(1);
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end else if (pop) begin
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wr_ptr <= wr_ptr - ADDRW'(is_part[rd_ptr]);
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rd_ptr <= rd_ptr - ADDRW'(is_part[rd_ptr]);
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end
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end
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end
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VX_dp_ram #(
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.DATAW(WIDTH * 2),
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.SIZE(DEPTH),
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.RWCHECK(1),
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.FASTRAM(1)
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) store (
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.clk(clk),
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.waddr(wr_ptr),
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.raddr(rd_ptr),
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.wren(push),
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.byteen(1'b1),
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.rden(pop),
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.din({q2, q1}),
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.dout({d2, d1})
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);
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always @(posedge clk) begin
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if (push) begin
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is_part[wr_ptr] <= 0;
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end else if (pop) begin
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is_part[rd_ptr] <= 1;
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end
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end
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wire p = is_part[rd_ptr];
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assign d = p ? d1 : d2;
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assign empty = ~(| wr_ptr);
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assign full = (ADDRW'(DEPTH-1) == wr_ptr);
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endmodule |