67 lines
2.7 KiB
Verilog
67 lines
2.7 KiB
Verilog
`include "VX_cache_config.v"
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module VX_cache_wb_sel_merge (
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// Per Bank WB
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input wire [`NUMBER_BANKS-1:0] per_bank_wb_valid,
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input wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid,
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input wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd,
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input wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb,
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input wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num,
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input wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data,
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output wire [`NUMBER_BANKS-1:0] per_bank_wb_pop,
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// Core Writeback
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input wire core_no_wb_slot,
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output reg [`NUMBER_REQUESTS-1:0] core_wb_valid,
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output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata,
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output wire [4:0] core_wb_req_rd,
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output wire [1:0] core_wb_req_wb,
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output wire [`NW_M1:0] core_wb_warp_num
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);
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reg [`NUMBER_BANKS-1:0] per_bank_wb_pop_unqual;
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assign per_bank_wb_pop = per_bank_wb_pop_unqual & {`NUMBER_BANKS{~core_no_wb_slot}};
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wire[`NUMBER_BANKS-1:0] bank_wants_wb;
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genvar curr_bank;
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generate
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for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin
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assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]);
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end
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endgenerate
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wire [(`vx_clog2(`NUMBER_BANKS))-1:0] main_bank_index;
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wire found_bank;
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VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_bank(
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.valids(bank_wants_wb),
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.index (main_bank_index),
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.found (found_bank)
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);
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assign core_wb_req_rd = per_bank_wb_rd [main_bank_index];
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assign core_wb_req_wb = per_bank_wb_wb [main_bank_index];
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assign core_wb_warp_num = per_bank_wb_warp_num[main_bank_index];
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integer this_bank;
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generate
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always @(*) begin
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core_wb_valid = 0;
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core_wb_readdata = 0;
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for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin
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if (found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin
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core_wb_valid[per_bank_wb_tid[this_bank]] = 1;
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core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
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per_bank_wb_pop_unqual[this_bank] = 1;
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end else begin
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per_bank_wb_pop_unqual[this_bank] = 0;
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end
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end
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end
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endgenerate
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endmodule |