46 lines
1.0 KiB
Verilog
46 lines
1.0 KiB
Verilog
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`include "../VX_define.v"
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`ifndef VX_FrE_to_BE_INTER
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`define VX_FrE_to_BE_INTER
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interface VX_frE_to_bckE_req_inter ();
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wire[11:0] csr_address;
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wire is_csr;
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wire csr_immed;
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wire[31:0] csr_mask;
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wire[4:0] rd;
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wire[4:0] rs1;
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wire[4:0] rs2;
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wire[4:0] alu_op;
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wire[1:0] wb;
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wire rs2_src;
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wire[31:0] itype_immed;
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wire[2:0] mem_read;
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wire[2:0] mem_write;
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wire[2:0] branch_type;
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wire[19:0] upper_immed;
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wire[31:0] curr_PC;
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/* verilator lint_off UNUSED */
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wire ebreak;
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/* verilator lint_on UNUSED */
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wire jalQual;
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wire jal;
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wire[31:0] jal_offset;
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wire[31:0] PC_next;
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wire[`NT_M1:0] valid;
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wire[`NW_M1:0] warp_num;
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// GPGPU stuff
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wire is_wspawn;
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wire is_tmc;
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wire is_split;
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wire is_barrier;
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endinterface
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`endif |