254 lines
8.8 KiB
Verilog
254 lines
8.8 KiB
Verilog
`include "VX_tex_define.vh"
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module VX_tex_memory #(
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parameter CORE_ID = 0,
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parameter REQ_INFO_WIDTH = 1
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) (
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input wire clk,
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input wire reset,
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// memory interface
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VX_dcache_core_req_if dcache_req_if,
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VX_dcache_core_rsp_if dcache_rsp_if,
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// inputs
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input wire req_valid,
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input wire [`NW_BITS-1:0] req_wid,
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input wire [`NUM_THREADS-1:0] req_tmask,
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input wire [31:0] req_PC,
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input wire [`TEX_FILTER_BITS-1:0] req_filter,
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input wire [`TEX_STRIDE_BITS-1:0] req_stride,
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input wire [`NUM_THREADS-1:0][3:0][31:0] req_addr,
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input wire [REQ_INFO_WIDTH-1:0] req_info,
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output wire req_ready,
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// outputs
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output wire rsp_valid,
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output wire [`NW_BITS-1:0] rsp_wid,
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output wire [`NUM_THREADS-1:0] rsp_tmask,
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output wire [31:0] rsp_PC,
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output wire [`TEX_FILTER_BITS-1:0] rsp_filter,
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output wire [`NUM_THREADS-1:0][3:0][31:0] rsp_data,
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output wire [REQ_INFO_WIDTH-1:0] rsp_info,
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input wire rsp_ready
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);
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`UNUSED_PARAM (CORE_ID)
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localparam RSP_CTR_W = $clog2(`NUM_THREADS * 4 + 1);
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wire [3:0] dup_reqs;
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wire [3:0][`NUM_THREADS-1:0][29:0] req_addr_w;
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wire [3:0][`NUM_THREADS-1:0][1:0] align_offs;
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// reorder address into quads
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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for (genvar j = 0; j < 4; ++j) begin
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assign req_addr_w[j][i] = req_addr[i][j][31:2];
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assign align_offs[j][i] = req_addr[i][j][1:0];
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end
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end
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// find duplicate addresses
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for (genvar i = 0; i < 4; ++i) begin
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wire [`NUM_THREADS-1:0] addr_matches;
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for (genvar j = 0; j < `NUM_THREADS; j++) begin
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assign addr_matches[j] = (req_addr_w[i][0] == req_addr_w[i][j]) || ~req_tmask[j];
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end
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assign dup_reqs[i] = req_tmask[0] && (& addr_matches);
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end
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// save request addresses into fifo
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wire reqq_push, reqq_pop, reqq_empty, reqq_full;
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wire [3:0][`NUM_THREADS-1:0][29:0] q_req_addr;
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wire [`NW_BITS-1:0] q_req_wid;
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wire [`NUM_THREADS-1:0] q_req_tmask;
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wire [31:0] q_req_PC;
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wire [`TEX_FILTER_BITS-1:0] q_req_filter;
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wire [REQ_INFO_WIDTH-1:0] q_req_info;
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wire [`TEX_STRIDE_BITS-1:0] q_req_stride;
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wire [3:0][`NUM_THREADS-1:0][1:0] q_align_offs;
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wire [3:0] q_dup_reqs;
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assign reqq_push = req_valid && req_ready;
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VX_fifo_queue #(
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.DATAW ((`NUM_THREADS * 4 * 30) + `NW_BITS + `NUM_THREADS + 32 + REQ_INFO_WIDTH + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (4 * `NUM_THREADS * 2) + 4),
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.SIZE (`LSUQ_SIZE),
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.BUFFERED (1)
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) req_queue (
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.clk (clk),
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.reset (reset),
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.push (reqq_push),
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.pop (reqq_pop),
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.data_in ({req_addr_w, req_wid, req_tmask, req_PC, req_info, req_filter, req_stride, align_offs, dup_reqs}),
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.data_out ({q_req_addr, q_req_wid, q_req_tmask, q_req_PC, q_req_info, q_req_filter, q_req_stride, q_align_offs, q_dup_reqs}),
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.empty (reqq_empty),
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.full (reqq_full),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (size)
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);
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// can take more requests?
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assign req_ready = ~reqq_full;
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///////////////////////////////////////////////////////////////////////////
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wire [`NUM_THREADS-1:0][29:0] texel_addr;
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wire texel_valid, texel_sent, last_texel_sent;
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wire texel_is_dup;
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reg [1:0] texel_idx;
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always @(posedge clk) begin
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if (reset || last_texel_sent) begin
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texel_idx <= 0;
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end else if (texel_sent) begin
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texel_idx <= texel_idx + 1;
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end
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end
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assign texel_valid = ~reqq_empty;
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assign texel_addr = q_req_addr[texel_idx];
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assign texel_is_dup = q_dup_reqs[texel_idx];
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wire is_last_texel = (texel_idx == (q_req_filter ? 3 : 0));
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assign last_texel_sent = texel_sent && is_last_texel;
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// DCache Request
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reg [`NUM_THREADS-1:0] texel_sent_mask;
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wire [`NUM_THREADS-1:0] dcache_req_fire;
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wire [`NUM_THREADS-1:0] dup_mask;
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assign dcache_req_fire = dcache_req_if.valid & dcache_req_if.ready;
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assign texel_sent = (&(dcache_req_if.ready | texel_sent_mask | ~q_req_tmask))
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|| (texel_is_dup & dcache_req_if.ready[0]);
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always @(posedge clk) begin
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if (reset || texel_sent) begin
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texel_sent_mask <= 0;
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end else begin
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texel_sent_mask <= texel_sent_mask | dcache_req_fire;
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end
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end
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assign dup_mask = {{(`NUM_THREADS-1){~texel_is_dup}}, 1'b1};
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assign dcache_req_if.valid = {`NUM_THREADS{texel_valid}} & q_req_tmask & dup_mask & ~texel_sent_mask;
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assign dcache_req_if.rw = {`NUM_THREADS{1'b0}};
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assign dcache_req_if.addr = texel_addr;
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assign dcache_req_if.byteen = {`NUM_THREADS{4'b1111}};
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assign dcache_req_if.data = 'x;
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`ifdef DBG_CACHE_REQ_INFO
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assign dcache_req_if.tag = {`NUM_THREADS{q_req_PC, q_req_wid, texel_idx}};
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`else
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assign dcache_req_if.tag = {`NUM_THREADS{texel_idx}};
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`UNUSED_VAR (q_req_wid)
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`UNUSED_VAR (q_req_PC)
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`endif
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// Dcache Response
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reg [3:0][`NUM_THREADS-1:0][31:0] rsp_texels, rsp_texels_n;
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reg [`NUM_THREADS-1:0][31:0] rsp_cur_data;
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reg [RSP_CTR_W-1:0] rsp_rem_ctr;
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wire [`NUM_THREADS-1:0] rsp_cur_tmask;
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wire [RSP_CTR_W-1:0] rsp_max_cnt;
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wire [$clog2(`NUM_THREADS + 1)-1:0] rsp_cur_cnt;
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wire dcache_rsp_fire;
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wire [1:0] rsp_texel_idx;
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wire rsp_is_dup;
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assign rsp_texel_idx = dcache_rsp_if.tag[1:0];
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assign rsp_is_dup = q_dup_reqs[rsp_texel_idx];
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assign dcache_rsp_fire = (| dcache_rsp_if.valid) && dcache_rsp_if.ready;
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assign rsp_cur_tmask = rsp_is_dup ? q_req_tmask : dcache_rsp_if.valid;
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assign rsp_cur_cnt = $countones(rsp_cur_tmask);
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assign rsp_max_cnt = $countones(q_req_tmask) * (q_req_filter ? 4 : 1);
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [31:0] src_data = (i == 0 || rsp_is_dup) ? dcache_rsp_if.data[0] : dcache_rsp_if.data[i];
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reg [31:0] rsp_data_shifted;
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always @(*) begin
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rsp_data_shifted[31:16] = src_data[31:16];
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rsp_data_shifted[15:0] = q_align_offs[rsp_texel_idx][i][1] ? src_data[31:16] : src_data[15:0];
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rsp_data_shifted[7:0] = q_align_offs[rsp_texel_idx][i][0] ? rsp_data_shifted[15:8] : rsp_data_shifted[7:0];
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end
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always @(*) begin
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case (q_req_stride)
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0: rsp_cur_data[i] = 32'(rsp_data_shifted[7:0]);
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1: rsp_cur_data[i] = 32'(rsp_data_shifted[15:0]);
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default: rsp_cur_data[i] = rsp_data_shifted;
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endcase
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end
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end
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always @(*) begin
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rsp_texels_n = rsp_texels;
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rsp_texels_n[rsp_texel_idx] |= rsp_cur_data;
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end
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always @(posedge clk) begin
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if (reset || reqq_pop) begin
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rsp_texels <= '0;
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end else if (dcache_rsp_fire) begin
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rsp_texels <= rsp_texels_n;
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end
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end
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always @(posedge clk) begin
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if ((| dcache_req_fire) && ~(| rsp_rem_ctr)) begin
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rsp_rem_ctr <= rsp_max_cnt;
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end else if (dcache_rsp_fire) begin
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rsp_rem_ctr <= rsp_rem_ctr - RSP_CTR_W'(rsp_cur_cnt);
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end
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end
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wire stall_out = rsp_valid && ~rsp_ready;
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wire texel_done = dcache_rsp_fire && (rsp_rem_ctr == RSP_CTR_W'(rsp_cur_cnt));
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assign reqq_pop = texel_done && ~stall_out;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `TEX_FILTER_BITS + (4 * `NUM_THREADS * 32) + REQ_INFO_WIDTH),
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.RESETW (1)
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) rsp_pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({texel_done, q_req_wid, q_req_tmask, q_req_PC, q_req_filter, rsp_texels_n, q_req_info}),
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.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_filter, rsp_data, rsp_info})
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);
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// Can accept new cache response?
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assign dcache_rsp_if.ready = ~stall_out || (rsp_rem_ctr != RSP_CTR_W'(rsp_cur_cnt));
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`ifdef DBG_PRINT_TEX
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always @(posedge clk) begin
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if ((| dcache_req_fire)) begin
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$display("%t: T$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, is_dup=%b",
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$time, CORE_ID, q_req_wid, q_req_PC, dcache_req_fire, texel_addr, dcache_req_if.tag, texel_is_dup);
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end
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if (dcache_rsp_fire) begin
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$display("%t: T$%0d Rsp: valid=%b, wid=%0d, PC=%0h, tag=%0h, data=%0h, is_dup=%b",
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$time, CORE_ID, dcache_rsp_if.valid, rsp_wid, rsp_PC, dcache_rsp_if.tag, dcache_rsp_if.data, rsp_is_dup);
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end
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end
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`endif
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endmodule
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