66 lines
1.2 KiB
C++
66 lines
1.2 KiB
C++
#include "cachesim.h"
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#include <iostream>
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#include <fstream>
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#include <iomanip>
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#define VCD_OUTPUT 1
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int main(int argc, char **argv)
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{
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//init
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RAM ram;
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CacheSim cachesim;
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cachesim.attach_ram(&ram);
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unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
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unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
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//write req
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core_req_t* write = new core_req_t;
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write->valid = 0xf;
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write->rw = 0xf;
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write->byteen = 0xffff;
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write->addr = addr;
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write->data = data;
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write->tag = 0xff;
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//read req
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core_req_t* read = new core_req_t;
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read->valid = 0xf;
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read->rw = 0;
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read->byteen = 0xffff;
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read->addr = addr;
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read->data = addr;
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read->tag = 0xff;
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// reset the device
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cachesim.reset();
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//queue reqs
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cachesim.send_req(write);
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cachesim.send_req(read);
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cachesim.step();
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//cachesim.get_core_req();
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//write block to cache
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// cachesim.set_core_req();
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for (int i = 0; i < 100; ++i){
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/*if(i == 1){
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cachesim.clear_req();
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}*/
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cachesim.step();
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}
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cachesim.get_core_req();
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// read block
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//cachesim.set_core_req2();
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for (int i = 0; i < 100; ++i){
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if(i == 1){
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//read block from cache
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cachesim.clear_req();
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}
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cachesim.step();
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}
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return 0;
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}
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