31 lines
399 B
Verilog
31 lines
399 B
Verilog
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module VX_generic_register
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#(
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parameter N = 1
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)
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(
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input clk,
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input reset,
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input stall,
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input flush,
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input[N-1:0] in,
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output [N-1:0] out
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);
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reg[N-1:0] value;
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always @(posedge clk or posedge reset) begin
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if (reset || flush) begin
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value <= 0;
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end else if (~stall) begin
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value <= in;
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end
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end
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assign out = value;
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endmodule |