c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
702 lines
23 KiB
C++
702 lines
23 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <iostream>
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#include <iomanip>
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#include <string.h>
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#include <assert.h>
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#include <util.h>
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#include "types.h"
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#include "arch.h"
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#include "mem.h"
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#include "decode.h"
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#include "core.h"
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#include "debug.h"
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#include "constants.h"
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#include "processor_impl.h"
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using namespace vortex;
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Core::Core(const SimContext& ctx,
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uint32_t core_id,
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Cluster* cluster,
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const Arch &arch,
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const DCRS &dcrs,
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SharedMem::Ptr sharedmem)
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: SimObject(ctx, "core")
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, icache_req_ports(1, this)
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, icache_rsp_ports(1, this)
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, dcache_req_ports(NUM_LSU_LANES, this)
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, dcache_rsp_ports(NUM_LSU_LANES, this)
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, core_id_(core_id)
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, arch_(arch)
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, dcrs_(dcrs)
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, decoder_(arch)
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, warps_(arch.num_warps())
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, barriers_(arch.num_barriers(), 0)
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, fcsrs_(arch.num_warps(), 0)
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, ibuffers_(ISSUE_WIDTH, IBUF_SIZE)
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, scoreboard_(arch_)
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, operands_(ISSUE_WIDTH)
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, dispatchers_((uint32_t)ExeType::MAX)
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, exe_units_((uint32_t)ExeType::MAX)
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, sharedmem_(sharedmem)
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, fetch_latch_("fetch")
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, decode_latch_("decode")
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, pending_icache_(arch_.num_warps())
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, committed_traces_(ISSUE_WIDTH, nullptr)
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, csrs_(arch.num_warps())
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, cluster_(cluster)
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{
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for (uint32_t i = 0; i < arch_.num_warps(); ++i) {
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csrs_.at(i).resize(arch.num_threads());
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}
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for (uint32_t i = 0; i < arch_.num_warps(); ++i) {
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warps_.at(i) = std::make_shared<Warp>(this, i);
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}
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for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
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operands_.at(i) = SimPlatform::instance().create_object<Operand>();
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}
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// initialize dispatchers
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dispatchers_.at((int)ExeType::ALU) = SimPlatform::instance().create_object<Dispatcher>(arch, 2, NUM_ALU_BLOCKS, NUM_ALU_LANES);
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dispatchers_.at((int)ExeType::FPU) = SimPlatform::instance().create_object<Dispatcher>(arch, 2, NUM_FPU_BLOCKS, NUM_FPU_LANES);
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dispatchers_.at((int)ExeType::LSU) = SimPlatform::instance().create_object<Dispatcher>(arch, 2, 1, NUM_LSU_LANES);
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dispatchers_.at((int)ExeType::SFU) = SimPlatform::instance().create_object<Dispatcher>(arch, 2, 1, NUM_SFU_LANES);
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// initialize execute units
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exe_units_.at((int)ExeType::ALU) = SimPlatform::instance().create_object<AluUnit>(this);
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exe_units_.at((int)ExeType::FPU) = SimPlatform::instance().create_object<FpuUnit>(this);
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exe_units_.at((int)ExeType::LSU) = SimPlatform::instance().create_object<LsuUnit>(this);
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exe_units_.at((int)ExeType::SFU) = SimPlatform::instance().create_object<SfuUnit>(this);
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this->reset();
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}
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Core::~Core() {
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this->cout_flush();
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}
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void Core::reset() {
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for (auto& warp : warps_) {
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warp->reset();
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}
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warps_.at(0)->setTmask(0, true);
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active_warps_ = 1;
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for (auto& exe_unit : exe_units_) {
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exe_unit->reset();
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}
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for ( auto& barrier : barriers_) {
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barrier.reset();
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}
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for (auto& fcsr : fcsrs_) {
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fcsr = 0;
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}
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for (auto& ibuf : ibuffers_) {
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ibuf.clear();
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}
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commit_exe_= 0;
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scoreboard_.clear();
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fetch_latch_.clear();
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decode_latch_.clear();
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pending_icache_.clear();
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stalled_warps_.reset();
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issued_instrs_ = 0;
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committed_instrs_ = 0;
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exited_ = false;
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perf_stats_ = PerfStats();
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pending_ifetches_ = 0;
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}
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void Core::tick() {
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this->commit();
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this->execute();
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this->issue();
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this->decode();
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this->fetch();
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this->schedule();
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++perf_stats_.cycles;
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DPN(2, std::flush);
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}
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void Core::schedule() {
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int scheduled_warp = -1;
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// find next ready warp
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for (size_t wid = 0, nw = arch_.num_warps(); wid < nw; ++wid) {
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bool warp_active = active_warps_.test(wid);
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bool warp_stalled = stalled_warps_.test(wid);
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if (warp_active && !warp_stalled) {
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scheduled_warp = wid;
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break;
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}
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}
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if (scheduled_warp == -1)
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return;
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// suspend warp until decode
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stalled_warps_.set(scheduled_warp);
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// evaluate scheduled warp
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auto& warp = warps_.at(scheduled_warp);
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auto trace = warp->eval();
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DT(3, "pipeline-schedule: " << *trace);
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// advance to fetch stage
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fetch_latch_.push(trace);
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++issued_instrs_;
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}
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void Core::fetch() {
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perf_stats_.ifetch_latency += pending_ifetches_;
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// handle icache reponse
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auto& icache_rsp_port = icache_rsp_ports.at(0);
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if (!icache_rsp_port.empty()){
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auto& mem_rsp = icache_rsp_port.front();
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auto trace = pending_icache_.at(mem_rsp.tag);
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decode_latch_.push(trace);
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DT(3, "icache-rsp: addr=0x" << std::hex << trace->PC << ", tag=" << mem_rsp.tag << ", " << *trace);
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pending_icache_.release(mem_rsp.tag);
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icache_rsp_port.pop();
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--pending_ifetches_;
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}
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// send icache request
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if (fetch_latch_.empty())
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return;
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auto trace = fetch_latch_.front();
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MemReq mem_req;
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mem_req.addr = trace->PC;
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mem_req.write = false;
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mem_req.tag = pending_icache_.allocate(trace);
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mem_req.cid = trace->cid;
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mem_req.uuid = trace->uuid;
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icache_req_ports.at(0).send(mem_req, 1);
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DT(3, "icache-req: addr=0x" << std::hex << mem_req.addr << ", tag=" << mem_req.tag << ", " << *trace);
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fetch_latch_.pop();
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++pending_ifetches_;
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++perf_stats_.ifetches;
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}
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void Core::decode() {
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if (decode_latch_.empty())
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return;
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auto trace = decode_latch_.front();
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// check ibuffer capacity
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auto& ibuffer = ibuffers_.at(trace->wid % ISSUE_WIDTH);
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if (ibuffer.full()) {
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if (!trace->log_once(true)) {
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DT(3, "*** ibuffer-stall: " << *trace);
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}
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++perf_stats_.ibuf_stalls;
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return;
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} else {
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trace->log_once(false);
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}
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// release warp
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if (!trace->fetch_stall) {
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assert(stalled_warps_.test(trace->wid));
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stalled_warps_.reset(trace->wid);
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}
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// update perf counters
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uint32_t active_threads = trace->tmask.count();
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if (trace->exe_type == ExeType::LSU && trace->lsu_type == LsuType::LOAD)
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perf_stats_.loads += active_threads;
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if (trace->exe_type == ExeType::LSU && trace->lsu_type == LsuType::STORE)
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perf_stats_.stores += active_threads;
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DT(3, "pipeline-decode: " << *trace);
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// insert to ibuffer
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ibuffer.push(trace);
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decode_latch_.pop();
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}
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void Core::issue() {
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// operands to dispatch
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for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
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auto& operand = operands_.at(i);
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if (operand->Output.empty())
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continue;
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auto trace = operand->Output.front();
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if (dispatchers_.at((int)trace->exe_type)->push(i, trace)) {
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operand->Output.pop();
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trace->log_once(false);
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} else {
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if (!trace->log_once(true)) {
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DT(3, "*** dispatch-stall: " << *trace);
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}
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}
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}
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// issue ibuffer instructions
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for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
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auto& ibuffer = ibuffers_.at(i);
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if (ibuffer.empty())
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continue;
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auto trace = ibuffer.top();
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// check scoreboard
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if (scoreboard_.in_use(trace)) {
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if (!trace->log_once(true)) {
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DTH(3, "*** scoreboard-stall: dependents={");
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auto uses = scoreboard_.get_uses(trace);
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for (uint32_t j = 0, n = uses.size(); j < n; ++j) {
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auto& use = uses.at(j);
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__unused (use);
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if (j) DTN(3, ", ");
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DTN(3, use.type << use.reg << "(#" << use.owner << ")");
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}
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DTN(3, "}, " << *trace << std::endl);
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}
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++perf_stats_.scrb_stalls;
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continue;
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} else {
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trace->log_once(false);
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}
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// update scoreboard
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if (trace->wb) {
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scoreboard_.reserve(trace);
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}
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DT(3, "pipeline-scoreboard: " << *trace);
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// to operand stage
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operands_.at(i)->Input.send(trace, 1);
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ibuffer.pop();
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}
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}
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void Core::execute() {
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for (uint32_t i = 0; i < (uint32_t)ExeType::MAX; ++i) {
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auto& dispatch = dispatchers_.at(i);
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auto& exe_unit = exe_units_.at(i);
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for (uint32_t j = 0; j < ISSUE_WIDTH; ++j) {
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if (dispatch->Outputs.at(j).empty())
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continue;
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auto trace = dispatch->Outputs.at(j).front();
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exe_unit->Inputs.at(j).send(trace, 1);
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dispatch->Outputs.at(j).pop();
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}
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}
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}
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void Core::commit() {
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// process completed instructions
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for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
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auto trace = committed_traces_.at(i);
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if (!trace)
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continue;
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committed_traces_.at(i) = nullptr;
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// advance to commit stage
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DT(3, "pipeline-commit: " << *trace);
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assert(trace->cid == core_id_);
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// update scoreboard
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if (trace->eop) {
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if (trace->wb) {
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scoreboard_.release(trace);
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}
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assert(committed_instrs_ <= issued_instrs_);
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++committed_instrs_;
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perf_stats_.instrs += trace->tmask.count();
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}
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// delete the trace
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delete trace;
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}
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// select completed instructions
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for (uint32_t i = 0; i < (uint32_t)ExeType::MAX; ++i) {
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uint32_t ii = (commit_exe_ + i) % (uint32_t)ExeType::MAX;
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auto& exe_unit = exe_units_.at(ii);
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for (uint32_t j = 0; j < ISSUE_WIDTH; ++j) {
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auto committed_trace = committed_traces_.at(j);
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if (committed_trace)
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continue;
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auto& output = exe_unit->Outputs.at(j);
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if (output.empty())
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continue;
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auto trace = output.front();
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committed_traces_.at(j) = trace;
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output.pop();
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}
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}
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++commit_exe_;
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}
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void Core::wspawn(uint32_t num_warps, Word nextPC) {
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uint32_t active_warps = std::min<uint32_t>(num_warps, arch_.num_warps());
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DP(3, "*** Activate " << (active_warps-1) << " warps at PC: " << std::hex << nextPC);
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for (uint32_t i = 1; i < active_warps; ++i) {
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auto warp = warps_.at(i);
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warp->setPC(nextPC);
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warp->setTmask(0, true);
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active_warps_.set(i);
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}
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}
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void Core::barrier(uint32_t bar_id, uint32_t count, uint32_t warp_id) {
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uint32_t bar_idx = bar_id & 0x7fffffff;
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bool is_global = (bar_id >> 31);
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auto& barrier = barriers_.at(bar_idx);
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barrier.set(warp_id);
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DP(3, "*** Suspend core #" << core_id_ << ", warp #" << warp_id << " at barrier #" << bar_idx);
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if (is_global) {
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// global barrier handling
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if (barrier.count() == active_warps_.count()) {
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cluster_->barrier(bar_idx, count, core_id_);
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barrier.reset();
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}
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} else {
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// local barrier handling
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if (barrier.count() == (size_t)count) {
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// resume suspended warps
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for (uint32_t i = 0; i < arch_.num_warps(); ++i) {
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if (barrier.test(i)) {
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DP(3, "*** Resume core #" << core_id_ << ", warp #" << i << " at barrier #" << bar_idx);
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stalled_warps_.reset(i);
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}
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}
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barrier.reset();
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}
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}
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}
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void Core::icache_read(void *data, uint64_t addr, uint32_t size) {
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mmu_.read(data, addr, size, 0);
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}
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AddrType Core::get_addr_type(uint64_t addr) {
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if (SM_ENABLED) {
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if (addr >= SMEM_BASE_ADDR && addr < (SMEM_BASE_ADDR + (1 << SMEM_LOG_SIZE))) {
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return AddrType::Shared;
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}
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}
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if (addr >= IO_BASE_ADDR) {
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return AddrType::IO;
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}
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return AddrType::Global;
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}
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void Core::dcache_read(void *data, uint64_t addr, uint32_t size) {
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auto type = this->get_addr_type(addr);
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if (type == AddrType::Shared) {
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sharedmem_->read(data, addr, size);
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} else {
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mmu_.read(data, addr, size, 0);
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}
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DPH(2, "Mem Read: addr=0x" << std::hex << addr << ", data=0x" << ByteStream(data, size) << " (size=" << size << ", type=" << type << ")" << std::endl);
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}
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void Core::dcache_write(const void* data, uint64_t addr, uint32_t size) {
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auto type = this->get_addr_type(addr);
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if (addr >= uint64_t(IO_COUT_ADDR)
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&& addr < (uint64_t(IO_COUT_ADDR) + IO_COUT_SIZE)) {
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this->writeToStdOut(data, addr, size);
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} else {
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if (type == AddrType::Shared) {
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sharedmem_->write(data, addr, size);
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} else {
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mmu_.write(data, addr, size, 0);
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}
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}
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DPH(2, "Mem Write: addr=0x" << std::hex << addr << ", data=0x" << ByteStream(data, size) << " (size=" << size << ", type=" << type << ")" << std::endl);
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}
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void Core::dcache_amo_reserve(uint64_t addr) {
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auto type = this->get_addr_type(addr);
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if (type == AddrType::Global) {
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mmu_.amo_reserve(addr);
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}
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}
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bool Core::dcache_amo_check(uint64_t addr) {
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auto type = this->get_addr_type(addr);
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if (type == AddrType::Global) {
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return mmu_.amo_check(addr);
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}
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return false;
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}
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void Core::writeToStdOut(const void* data, uint64_t addr, uint32_t size) {
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if (size != 1)
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std::abort();
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uint32_t tid = (addr - IO_COUT_ADDR) & (IO_COUT_SIZE-1);
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auto& ss_buf = print_bufs_[tid];
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char c = *(char*)data;
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ss_buf << c;
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if (c == '\n') {
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std::cout << std::dec << "#" << tid << ": " << ss_buf.str() << std::flush;
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ss_buf.str("");
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}
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}
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void Core::cout_flush() {
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for (auto& buf : print_bufs_) {
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auto str = buf.second.str();
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if (!str.empty()) {
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std::cout << "#" << buf.first << ": " << str << std::endl;
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}
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}
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}
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uint32_t Core::get_csr(uint32_t addr, uint32_t tid, uint32_t wid) {
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switch (addr) {
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case VX_CSR_SATP:
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case VX_CSR_PMPCFG0:
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case VX_CSR_PMPADDR0:
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case VX_CSR_MSTATUS:
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case VX_CSR_MISA:
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case VX_CSR_MEDELEG:
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case VX_CSR_MIDELEG:
|
|
case VX_CSR_MIE:
|
|
case VX_CSR_MTVEC:
|
|
case VX_CSR_MEPC:
|
|
case VX_CSR_MNSTATUS:
|
|
return 0;
|
|
|
|
case VX_CSR_FFLAGS:
|
|
return fcsrs_.at(wid) & 0x1F;
|
|
case VX_CSR_FRM:
|
|
return (fcsrs_.at(wid) >> 5);
|
|
case VX_CSR_FCSR:
|
|
return fcsrs_.at(wid);
|
|
case VX_CSR_MHARTID: // global thread ID
|
|
return (core_id_ * arch_.num_warps() + wid) * arch_.num_threads() + tid;
|
|
case VX_CSR_THREAD_ID: // thread ID
|
|
return tid;
|
|
case VX_CSR_WARP_ID: // warp ID
|
|
return wid;
|
|
case VX_CSR_CORE_ID: // core ID
|
|
return core_id_;
|
|
case VX_CSR_THREAD_MASK: // thread mask
|
|
return warps_.at(wid)->getTmask();
|
|
case VX_CSR_WARP_MASK: // active warps
|
|
return active_warps_.to_ulong();
|
|
case VX_CSR_NUM_THREADS: // Number of threads per warp
|
|
return arch_.num_threads();
|
|
case VX_CSR_NUM_WARPS: // Number of warps per core
|
|
return arch_.num_warps();
|
|
case VX_CSR_NUM_CORES: // Number of cores per cluster
|
|
return uint32_t(arch_.num_cores()) * arch_.num_clusters();
|
|
case VX_CSR_MCYCLE: // NumCycles
|
|
return perf_stats_.cycles & 0xffffffff;
|
|
case VX_CSR_MCYCLE_H: // NumCycles
|
|
return (uint32_t)(perf_stats_.cycles >> 32);
|
|
case VX_CSR_MINSTRET: // NumInsts
|
|
return perf_stats_.instrs & 0xffffffff;
|
|
case VX_CSR_MINSTRET_H: // NumInsts
|
|
return (uint32_t)(perf_stats_.instrs >> 32);
|
|
default:
|
|
if ((addr >= VX_CSR_MPM_BASE && addr < (VX_CSR_MPM_BASE + 32))
|
|
|| (addr >= VX_CSR_MPM_BASE_H && addr < (VX_CSR_MPM_BASE_H + 32))) {
|
|
// user-defined MPM CSRs
|
|
auto perf_class = dcrs_.base_dcrs.read(VX_DCR_BASE_MPM_CLASS);
|
|
switch (perf_class) {
|
|
case VX_DCR_MPM_CLASS_NONE:
|
|
break;
|
|
case VX_DCR_MPM_CLASS_CORE: {
|
|
switch (addr) {
|
|
case VX_CSR_MPM_IBUF_ST: return perf_stats_.ibuf_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_IBUF_ST_H: return perf_stats_.ibuf_stalls >> 32;
|
|
case VX_CSR_MPM_SCRB_ST: return perf_stats_.scrb_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_SCRB_ST_H: return perf_stats_.scrb_stalls >> 32;
|
|
case VX_CSR_MPM_ALU_ST: return perf_stats_.alu_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_ALU_ST_H: return perf_stats_.alu_stalls >> 32;
|
|
case VX_CSR_MPM_LSU_ST: return perf_stats_.lsu_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_LSU_ST_H: return perf_stats_.lsu_stalls >> 32;
|
|
case VX_CSR_MPM_FPU_ST: return perf_stats_.fpu_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_FPU_ST_H: return perf_stats_.fpu_stalls >> 32;
|
|
case VX_CSR_MPM_SFU_ST: return perf_stats_.sfu_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_SFU_ST_H: return perf_stats_.sfu_stalls >> 32;
|
|
|
|
case VX_CSR_MPM_IFETCHES: return perf_stats_.ifetches & 0xffffffff;
|
|
case VX_CSR_MPM_IFETCHES_H: return perf_stats_.ifetches >> 32;
|
|
case VX_CSR_MPM_LOADS: return perf_stats_.loads & 0xffffffff;
|
|
case VX_CSR_MPM_LOADS_H: return perf_stats_.loads >> 32;
|
|
case VX_CSR_MPM_STORES: return perf_stats_.stores & 0xffffffff;
|
|
case VX_CSR_MPM_STORES_H: return perf_stats_.stores >> 32;
|
|
case VX_CSR_MPM_IFETCH_LAT: return perf_stats_.ifetch_latency & 0xffffffff;
|
|
case VX_CSR_MPM_IFETCH_LAT_H: return perf_stats_.ifetch_latency >> 32;
|
|
case VX_CSR_MPM_LOAD_LAT: return perf_stats_.load_latency & 0xffffffff;
|
|
case VX_CSR_MPM_LOAD_LAT_H: return perf_stats_.load_latency >> 32;
|
|
}
|
|
} break;
|
|
case VX_DCR_MPM_CLASS_MEM: {
|
|
auto proc_perf = cluster_->processor()->perf_stats();
|
|
switch (addr) {
|
|
case VX_CSR_MPM_ICACHE_READS: return proc_perf.clusters.icache.reads & 0xffffffff;
|
|
case VX_CSR_MPM_ICACHE_READS_H: return proc_perf.clusters.icache.reads >> 32;
|
|
case VX_CSR_MPM_ICACHE_MISS_R: return proc_perf.clusters.icache.read_misses & 0xffffffff;
|
|
case VX_CSR_MPM_ICACHE_MISS_R_H: return proc_perf.clusters.icache.read_misses >> 32;
|
|
|
|
case VX_CSR_MPM_DCACHE_READS: return proc_perf.clusters.dcache.reads & 0xffffffff;
|
|
case VX_CSR_MPM_DCACHE_READS_H: return proc_perf.clusters.dcache.reads >> 32;
|
|
case VX_CSR_MPM_DCACHE_WRITES: return proc_perf.clusters.dcache.writes & 0xffffffff;
|
|
case VX_CSR_MPM_DCACHE_WRITES_H: return proc_perf.clusters.dcache.writes >> 32;
|
|
case VX_CSR_MPM_DCACHE_MISS_R: return proc_perf.clusters.dcache.read_misses & 0xffffffff;
|
|
case VX_CSR_MPM_DCACHE_MISS_R_H: return proc_perf.clusters.dcache.read_misses >> 32;
|
|
case VX_CSR_MPM_DCACHE_MISS_W: return proc_perf.clusters.dcache.write_misses & 0xffffffff;
|
|
case VX_CSR_MPM_DCACHE_MISS_W_H: return proc_perf.clusters.dcache.write_misses >> 32;
|
|
case VX_CSR_MPM_DCACHE_BANK_ST: return proc_perf.clusters.dcache.bank_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_DCACHE_BANK_ST_H:return proc_perf.clusters.dcache.bank_stalls >> 32;
|
|
case VX_CSR_MPM_DCACHE_MSHR_ST: return proc_perf.clusters.dcache.mshr_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_DCACHE_MSHR_ST_H:return proc_perf.clusters.dcache.mshr_stalls >> 32;
|
|
|
|
case VX_CSR_MPM_SMEM_READS: return proc_perf.clusters.sharedmem.reads & 0xffffffff;
|
|
case VX_CSR_MPM_SMEM_READS_H: return proc_perf.clusters.sharedmem.reads >> 32;
|
|
case VX_CSR_MPM_SMEM_WRITES: return proc_perf.clusters.sharedmem.writes & 0xffffffff;
|
|
case VX_CSR_MPM_SMEM_WRITES_H: return proc_perf.clusters.sharedmem.writes >> 32;
|
|
case VX_CSR_MPM_SMEM_BANK_ST: return proc_perf.clusters.sharedmem.bank_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_SMEM_BANK_ST_H:return proc_perf.clusters.sharedmem.bank_stalls >> 32;
|
|
|
|
case VX_CSR_MPM_L2CACHE_READS: return proc_perf.clusters.l2cache.reads & 0xffffffff;
|
|
case VX_CSR_MPM_L2CACHE_READS_H: return proc_perf.clusters.l2cache.reads >> 32;
|
|
case VX_CSR_MPM_L2CACHE_WRITES: return proc_perf.clusters.l2cache.writes & 0xffffffff;
|
|
case VX_CSR_MPM_L2CACHE_WRITES_H: return proc_perf.clusters.l2cache.writes >> 32;
|
|
case VX_CSR_MPM_L2CACHE_MISS_R: return proc_perf.clusters.l2cache.read_misses & 0xffffffff;
|
|
case VX_CSR_MPM_L2CACHE_MISS_R_H: return proc_perf.clusters.l2cache.read_misses >> 32;
|
|
case VX_CSR_MPM_L2CACHE_MISS_W: return proc_perf.clusters.l2cache.write_misses & 0xffffffff;
|
|
case VX_CSR_MPM_L2CACHE_MISS_W_H: return proc_perf.clusters.l2cache.write_misses >> 32;
|
|
case VX_CSR_MPM_L2CACHE_BANK_ST: return proc_perf.clusters.l2cache.bank_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_L2CACHE_BANK_ST_H:return proc_perf.clusters.l2cache.bank_stalls >> 32;
|
|
case VX_CSR_MPM_L2CACHE_MSHR_ST: return proc_perf.clusters.l2cache.mshr_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_L2CACHE_MSHR_ST_H:return proc_perf.clusters.l2cache.mshr_stalls >> 32;
|
|
|
|
case VX_CSR_MPM_L3CACHE_READS: return proc_perf.l3cache.reads & 0xffffffff;
|
|
case VX_CSR_MPM_L3CACHE_READS_H: return proc_perf.l3cache.reads >> 32;
|
|
case VX_CSR_MPM_L3CACHE_WRITES: return proc_perf.l3cache.writes & 0xffffffff;
|
|
case VX_CSR_MPM_L3CACHE_WRITES_H: return proc_perf.l3cache.writes >> 32;
|
|
case VX_CSR_MPM_L3CACHE_MISS_R: return proc_perf.l3cache.read_misses & 0xffffffff;
|
|
case VX_CSR_MPM_L3CACHE_MISS_R_H: return proc_perf.l3cache.read_misses >> 32;
|
|
case VX_CSR_MPM_L3CACHE_MISS_W: return proc_perf.l3cache.write_misses & 0xffffffff;
|
|
case VX_CSR_MPM_L3CACHE_MISS_W_H: return proc_perf.l3cache.write_misses >> 32;
|
|
case VX_CSR_MPM_L3CACHE_BANK_ST: return proc_perf.l3cache.bank_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_L3CACHE_BANK_ST_H:return proc_perf.l3cache.bank_stalls >> 32;
|
|
case VX_CSR_MPM_L3CACHE_MSHR_ST: return proc_perf.l3cache.mshr_stalls & 0xffffffff;
|
|
case VX_CSR_MPM_L3CACHE_MSHR_ST_H:return proc_perf.l3cache.mshr_stalls >> 32;
|
|
|
|
case VX_CSR_MPM_MEM_READS: return proc_perf.mem_reads & 0xffffffff;
|
|
case VX_CSR_MPM_MEM_READS_H: return proc_perf.mem_reads >> 32;
|
|
case VX_CSR_MPM_MEM_WRITES: return proc_perf.mem_writes & 0xffffffff;
|
|
case VX_CSR_MPM_MEM_WRITES_H:return proc_perf.mem_writes >> 32;
|
|
case VX_CSR_MPM_MEM_LAT: return proc_perf.mem_latency & 0xffffffff;
|
|
case VX_CSR_MPM_MEM_LAT_H: return proc_perf.mem_latency >> 32;
|
|
}
|
|
} break;
|
|
}
|
|
} else {
|
|
std::cout << std::hex << "Error: invalid CSR read addr=0x" << addr << std::endl;
|
|
std::abort();
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void Core::set_csr(uint32_t addr, uint32_t value, uint32_t tid, uint32_t wid) {
|
|
__unused (tid);
|
|
switch (addr) {
|
|
case VX_CSR_FFLAGS:
|
|
fcsrs_.at(wid) = (fcsrs_.at(wid) & ~0x1F) | (value & 0x1F);
|
|
break;
|
|
case VX_CSR_FRM:
|
|
fcsrs_.at(wid) = (fcsrs_.at(wid) & ~0xE0) | (value << 5);
|
|
break;
|
|
case VX_CSR_FCSR:
|
|
fcsrs_.at(wid) = value & 0xff;
|
|
break;
|
|
case VX_CSR_SATP:
|
|
case VX_CSR_MSTATUS:
|
|
case VX_CSR_MEDELEG:
|
|
case VX_CSR_MIDELEG:
|
|
case VX_CSR_MIE:
|
|
case VX_CSR_MTVEC:
|
|
case VX_CSR_MEPC:
|
|
case VX_CSR_PMPCFG0:
|
|
case VX_CSR_PMPADDR0:
|
|
case VX_CSR_MNSTATUS:
|
|
break;
|
|
default:
|
|
{
|
|
std::cout << std::hex << "Error: invalid CSR write addr=0x" << addr << ", value=0x" << value << std::endl;
|
|
std::abort();
|
|
}
|
|
}
|
|
}
|
|
|
|
void Core::trigger_ecall() {
|
|
active_warps_.reset();
|
|
exited_ = true;
|
|
}
|
|
|
|
void Core::trigger_ebreak() {
|
|
active_warps_.reset();
|
|
exited_ = true;
|
|
}
|
|
|
|
bool Core::check_exit(Word* exitcode, bool riscv_test) const {
|
|
if (exited_) {
|
|
Word ec = warps_.at(0)->getIRegValue(3);
|
|
if (riscv_test) {
|
|
*exitcode = (1 - ec);
|
|
} else {
|
|
*exitcode = ec;
|
|
}
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool Core::running() const {
|
|
return (committed_instrs_ != issued_instrs_);
|
|
}
|
|
|
|
void Core::resume() {
|
|
stalled_warps_.reset();
|
|
}
|
|
|
|
void Core::attach_ram(RAM* ram) {
|
|
// bind RAM to memory unit
|
|
#if (XLEN == 64)
|
|
mmu_.attach(*ram, 0, 0xFFFFFFFFFFFFFFFF);
|
|
#else
|
|
mmu_.attach(*ram, 0, 0xFFFFFFFF);
|
|
#endif
|
|
}
|