c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
99 lines
3.3 KiB
Systemverilog
99 lines
3.3 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_serial_div #(
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parameter WIDTHN = 32,
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parameter WIDTHD = 32,
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parameter WIDTHQ = 32,
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parameter WIDTHR = 32,
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parameter LANES = 1
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) (
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input wire clk,
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input wire reset,
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input wire strobe,
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output wire busy,
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input wire is_signed,
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input wire [LANES-1:0][WIDTHN-1:0] numer,
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input wire [LANES-1:0][WIDTHD-1:0] denom,
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output wire [LANES-1:0][WIDTHQ-1:0] quotient,
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output wire [LANES-1:0][WIDTHR-1:0] remainder
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);
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localparam MIN_ND = (WIDTHN < WIDTHD) ? WIDTHN : WIDTHD;
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localparam CNTRW = `CLOG2(WIDTHN);
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reg [LANES-1:0][WIDTHN + MIN_ND:0] working;
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reg [LANES-1:0][WIDTHD-1:0] denom_r;
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wire [LANES-1:0][WIDTHN-1:0] numer_qual;
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wire [LANES-1:0][WIDTHD-1:0] denom_qual;
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wire [LANES-1:0][WIDTHD:0] sub_result;
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reg [LANES-1:0] inv_quot, inv_rem;
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reg [CNTRW-1:0] cntr;
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reg busy_r;
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for (genvar i = 0; i < LANES; ++i) begin
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wire negate_numer = is_signed && numer[i][WIDTHN-1];
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wire negate_denom = is_signed && denom[i][WIDTHD-1];
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assign numer_qual[i] = negate_numer ? -$signed(numer[i]) : numer[i];
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assign denom_qual[i] = negate_denom ? -$signed(denom[i]) : denom[i];
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assign sub_result[i] = working[i][WIDTHN + MIN_ND : WIDTHN] - denom_r[i];
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end
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always @(posedge clk) begin
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if (reset) begin
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busy_r <= 0;
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end else begin
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if (strobe) begin
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busy_r <= 1;
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end
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if (busy && cntr == 0) begin
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busy_r <= 0;
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end
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end
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cntr <= cntr - CNTRW'(1);
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if (strobe) begin
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cntr <= CNTRW'(WIDTHN-1);
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end
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end
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for (genvar i = 0; i < LANES; ++i) begin
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always @(posedge clk) begin
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if (strobe) begin
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working[i] <= {{WIDTHD{1'b0}}, numer_qual[i], 1'b0};
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denom_r[i] <= denom_qual[i];
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inv_quot[i] <= (denom[i] != 0) && is_signed && (numer[i][31] ^ denom[i][31]);
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inv_rem[i] <= is_signed && numer[i][31];
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end else if (busy_r) begin
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working[i] <= sub_result[i][WIDTHD] ? {working[i][WIDTHN+MIN_ND-1:0], 1'b0} :
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{sub_result[i][WIDTHD-1:0], working[i][WIDTHN-1:0], 1'b1};
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end
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end
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wire [WIDTHQ-1:0] q = working[i][WIDTHQ-1:0];
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wire [WIDTHR-1:0] r = working[i][WIDTHN+WIDTHR:WIDTHN+1];
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assign quotient[i] = inv_quot[i] ? -$signed(q) : q;
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assign remainder[i] = inv_rem[i] ? -$signed(r) : r;
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end
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assign busy = busy_r;
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endmodule
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`TRACING_ON
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