c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
112 lines
3.7 KiB
Systemverilog
112 lines
3.7 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_mem_rsp_sel #(
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parameter NUM_REQS = 1,
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parameter DATA_WIDTH = 1,
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parameter TAG_WIDTH = 1,
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parameter TAG_SEL_BITS = 0,
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parameter OUT_REG = 0
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) (
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input wire clk,
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input wire reset,
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// input response
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input wire [NUM_REQS-1:0] rsp_valid_in,
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input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_in,
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input wire [NUM_REQS-1:0][TAG_WIDTH-1:0] rsp_tag_in,
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output wire [NUM_REQS-1:0] rsp_ready_in,
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// output responses
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output wire rsp_valid_out,
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output wire [NUM_REQS-1:0] rsp_mask_out,
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output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_out,
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output wire [TAG_WIDTH-1:0] rsp_tag_out,
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input wire rsp_ready_out
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);
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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localparam LOG_NUM_REQS = `CLOG2(NUM_REQS);
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if (NUM_REQS > 1) begin
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wire [LOG_NUM_REQS-1:0] grant_index;
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wire grant_valid;
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wire rsp_fire;
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VX_priority_arbiter #(
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.NUM_REQS (NUM_REQS)
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) arbiter (
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.clk (clk),
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.reset (reset),
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.unlock (rsp_fire),
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.requests (rsp_valid_in),
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.grant_valid (grant_valid),
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.grant_index (grant_index),
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`UNUSED_PIN (grant_onehot)
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);
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reg [NUM_REQS-1:0] rsp_valid_sel;
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reg [NUM_REQS-1:0] rsp_ready_sel;
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wire rsp_ready_unqual;
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wire [TAG_WIDTH-1:0] rsp_tag_sel = rsp_tag_in[grant_index];
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always @(*) begin
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rsp_valid_sel = '0;
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rsp_ready_sel = '0;
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for (integer i = 0; i < NUM_REQS; ++i) begin
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if (rsp_tag_in[i][TAG_SEL_BITS-1:0] == rsp_tag_sel[TAG_SEL_BITS-1:0]) begin
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rsp_valid_sel[i] = rsp_valid_in[i];
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rsp_ready_sel[i] = rsp_ready_unqual;
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end
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end
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end
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assign rsp_fire = grant_valid && rsp_ready_unqual;
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VX_elastic_buffer #(
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.DATAW (NUM_REQS + TAG_WIDTH + (NUM_REQS * DATA_WIDTH)),
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.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
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.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
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) out_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (grant_valid),
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.data_in ({rsp_valid_sel, rsp_tag_sel, rsp_data_in}),
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.ready_in (rsp_ready_unqual),
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.valid_out (rsp_valid_out),
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.data_out ({rsp_mask_out, rsp_tag_out, rsp_data_out}),
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.ready_out (rsp_ready_out)
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);
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assign rsp_ready_in = rsp_ready_sel;
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end else begin
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assign rsp_valid_out = rsp_valid_in;
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assign rsp_mask_out = 1'b1;
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assign rsp_tag_out = rsp_tag_in;
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assign rsp_data_out = rsp_data_in;
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assign rsp_ready_in = rsp_ready_out;
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end
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endmodule
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`TRACING_ON
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