c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
212 lines
7.6 KiB
Systemverilog
212 lines
7.6 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`TRACING_OFF
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module VX_avs_adapter #(
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parameter DATA_WIDTH = 1,
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parameter ADDR_WIDTH = 1,
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parameter BURST_WIDTH = 1,
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parameter NUM_BANKS = 1,
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parameter TAG_WIDTH = 1,
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parameter RD_QUEUE_SIZE = 1,
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parameter OUT_REG_REQ = 0,
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parameter OUT_REG_RSP = 0
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) (
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input wire clk,
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input wire reset,
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// Memory request
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input wire mem_req_valid,
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input wire mem_req_rw,
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input wire [DATA_WIDTH/8-1:0] mem_req_byteen,
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input wire [ADDR_WIDTH-1:0] mem_req_addr,
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input wire [DATA_WIDTH-1:0] mem_req_data,
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input wire [TAG_WIDTH-1:0] mem_req_tag,
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output wire mem_req_ready,
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// Memory response
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output wire mem_rsp_valid,
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output wire [DATA_WIDTH-1:0] mem_rsp_data,
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output wire [TAG_WIDTH-1:0] mem_rsp_tag,
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input wire mem_rsp_ready,
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// AVS bus
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output wire [DATA_WIDTH-1:0] avs_writedata [NUM_BANKS],
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input wire [DATA_WIDTH-1:0] avs_readdata [NUM_BANKS],
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output wire [ADDR_WIDTH-1:0] avs_address [NUM_BANKS],
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input wire avs_waitrequest [NUM_BANKS],
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output wire avs_write [NUM_BANKS],
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output wire avs_read [NUM_BANKS],
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output wire [DATA_WIDTH/8-1:0] avs_byteenable [NUM_BANKS],
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output wire [BURST_WIDTH-1:0] avs_burstcount [NUM_BANKS],
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input wire avs_readdatavalid [NUM_BANKS]
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);
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localparam DATA_SIZE = DATA_WIDTH/8;
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localparam RD_QUEUE_ADDR_WIDTH = `CLOG2(RD_QUEUE_SIZE+1);
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localparam BANK_ADDRW = `LOG2UP(NUM_BANKS);
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localparam LOG2_NUM_BANKS = `CLOG2(NUM_BANKS);
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localparam BANK_OFFSETW = ADDR_WIDTH - LOG2_NUM_BANKS;
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// Requests handling //////////////////////////////////////////////////////
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wire [NUM_BANKS-1:0] req_queue_push, req_queue_pop;
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wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] req_queue_tag_out;
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wire [NUM_BANKS-1:0] req_queue_going_full;
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wire [NUM_BANKS-1:0][RD_QUEUE_ADDR_WIDTH-1:0] req_queue_size;
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wire [BANK_ADDRW-1:0] req_bank_sel;
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wire [BANK_OFFSETW-1:0] req_bank_off;
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wire [NUM_BANKS-1:0] bank_req_ready;
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if (NUM_BANKS > 1) begin
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assign req_bank_sel = mem_req_addr[BANK_ADDRW-1:0];
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end else begin
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assign req_bank_sel = '0;
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end
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assign req_bank_off = mem_req_addr[ADDR_WIDTH-1:LOG2_NUM_BANKS];
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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assign req_queue_push[i] = mem_req_valid && ~mem_req_rw && bank_req_ready[i] && (req_bank_sel == i);
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end
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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VX_pending_size #(
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.SIZE (RD_QUEUE_SIZE)
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) pending_size (
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.clk (clk),
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.reset (reset),
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.incr (req_queue_push[i]),
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.decr (req_queue_pop[i]),
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.full (req_queue_going_full[i]),
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.size (req_queue_size[i]),
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`UNUSED_PIN (empty)
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);
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`UNUSED_VAR (req_queue_size)
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VX_fifo_queue #(
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.DATAW (TAG_WIDTH),
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.DEPTH (RD_QUEUE_SIZE)
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) rd_req_queue (
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.clk (clk),
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.reset (reset),
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.push (req_queue_push[i]),
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.pop (req_queue_pop[i]),
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.data_in (mem_req_tag),
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.data_out (req_queue_tag_out[i]),
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`UNUSED_PIN (empty),
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`UNUSED_PIN (full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (size)
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);
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end
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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wire valid_out;
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wire rw_out;
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wire [DATA_SIZE-1:0] byteen_out;
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wire [BANK_OFFSETW-1:0] addr_out;
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wire [DATA_WIDTH-1:0] data_out;
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wire ready_out;
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wire valid_out_w = mem_req_valid && ~req_queue_going_full[i] && (req_bank_sel == i);
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wire ready_out_w;
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VX_elastic_buffer #(
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.DATAW (1 + DATA_SIZE + BANK_OFFSETW + DATA_WIDTH),
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.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG_REQ)),
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.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG_REQ))
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) req_out_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (valid_out_w),
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.ready_in (ready_out_w),
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.data_in ({mem_req_rw, mem_req_byteen, req_bank_off, mem_req_data}),
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.data_out ({rw_out, byteen_out, addr_out, data_out}),
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.valid_out (valid_out),
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.ready_out (ready_out)
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);
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assign avs_read[i] = valid_out && ~rw_out;
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assign avs_write[i] = valid_out && rw_out;
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assign avs_address[i] = ADDR_WIDTH'(addr_out);
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assign avs_byteenable[i] = byteen_out;
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assign avs_writedata[i] = data_out;
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assign avs_burstcount[i] = BURST_WIDTH'(1);
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assign ready_out = ~avs_waitrequest[i];
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assign bank_req_ready[i] = ready_out_w && ~req_queue_going_full[i];
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end
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if (NUM_BANKS > 1) begin
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assign mem_req_ready = bank_req_ready[req_bank_sel];
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end else begin
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assign mem_req_ready = bank_req_ready;
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end
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// Responses handling /////////////////////////////////////////////////////
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wire [NUM_BANKS-1:0] rsp_arb_valid_in;
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wire [NUM_BANKS-1:0][DATA_WIDTH+TAG_WIDTH-1:0] rsp_arb_data_in;
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wire [NUM_BANKS-1:0] rsp_arb_ready_in;
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wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] rsp_queue_data_out;
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wire [NUM_BANKS-1:0] rsp_queue_empty;
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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VX_fifo_queue #(
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.DATAW (DATA_WIDTH),
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.DEPTH (RD_QUEUE_SIZE)
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) rd_rsp_queue (
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.clk (clk),
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.reset (reset),
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.push (avs_readdatavalid[i]),
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.pop (req_queue_pop[i]),
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.data_in (avs_readdata[i]),
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.data_out (rsp_queue_data_out[i]),
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.empty (rsp_queue_empty[i]),
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`UNUSED_PIN (full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (size)
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);
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end
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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assign rsp_arb_valid_in[i] = !rsp_queue_empty[i];
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assign rsp_arb_data_in[i] = {rsp_queue_data_out[i], req_queue_tag_out[i]};
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assign req_queue_pop[i] = rsp_arb_valid_in[i] && rsp_arb_ready_in[i];
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end
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VX_stream_arb #(
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.NUM_INPUTS (NUM_BANKS),
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.DATAW (DATA_WIDTH + TAG_WIDTH),
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.ARBITER ("R"),
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.OUT_REG (OUT_REG_RSP)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (rsp_arb_valid_in),
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.data_in (rsp_arb_data_in),
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.ready_in (rsp_arb_ready_in),
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.data_out ({mem_rsp_data, mem_rsp_tag}),
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.valid_out (mem_rsp_valid),
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.ready_out (mem_rsp_ready),
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`UNUSED_PIN (sel_out)
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);
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endmodule
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`TRACING_ON
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