191 lines
7.4 KiB
Verilog
191 lines
7.4 KiB
Verilog
`include "VX_define.vh"
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`include "fpnew_pkg.sv"
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`include "defs_div_sqrt_mvp.sv"
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module VX_fpu_unit #(
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parameter CORE_ID = 0
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) (
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// inputs
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input wire clk,
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input wire reset,
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// inputs
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VX_fpu_req_if fpu_req_if,
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VX_csr_to_fpu_if csr_to_fpu_if,
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// outputs
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VX_fpu_to_cmt_if fpu_commit_if
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);
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localparam FOP_BITS = fpnew_pkg::OP_BITS;
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localparam FMTF_BITS = $clog2(fpnew_pkg::NUM_FP_FORMATS);
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localparam FMTI_BITS = $clog2(fpnew_pkg::NUM_INT_FORMATS);
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localparam int FPU_DPATHW = `NUM_THREADS * 32;
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localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
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Width: FPU_DPATHW,
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EnableVectors: 1,
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EnableNanBox: 1,
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FpFmtMask: 5'b10000,
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IntFmtMask: 4'b0010
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};
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localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
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PipeRegs:'{'{`LATENCY_FMULADD, 0, 0, 0, 0}, // ADDMUL
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'{default: `LATENCY_FDIVSQRT}, // DIVSQRT
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'{default: `LATENCY_FNONCOMP}, // NONCOMP
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'{default: `LATENCY_FCONV}}, // CONV
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UnitTypes:'{'{default: fpnew_pkg::PARALLEL}, // ADDMUL
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'{default: fpnew_pkg::MERGED}, // DIVSQRT
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'{default: fpnew_pkg::PARALLEL}, // NONCOMP
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'{default: fpnew_pkg::MERGED}}, // CONV
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PipeConfig: fpnew_pkg::DISTRIBUTED
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};
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wire fpu_in_ready, fpu_in_valid;
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wire fpu_out_ready, fpu_out_valid;
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reg [`LOG2UP(`FPURQ_SIZE)-1:0] fpu_in_tag, fpu_out_tag;
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reg [2:0][`NUM_THREADS-1:0][31:0] fpu_operands;
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wire [FMTF_BITS-1:0] fpu_src_fmt = fpnew_pkg::FP32;
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wire [FMTF_BITS-1:0] fpu_dst_fmt = fpnew_pkg::FP32;
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wire [FMTI_BITS-1:0] fpu_int_fmt = fpnew_pkg::INT32;
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wire [`NUM_THREADS-1:0][31:0] fpu_result;
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fpnew_pkg::status_t fpu_status;
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assign csr_to_fpu_if.warp_num = fpu_req_if.warp_num;
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wire [`FRM_BITS-1:0] real_frm = (fpu_req_if.frm == `FRM_DYN) ? csr_to_fpu_if.frm : fpu_req_if.frm;
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wire is_class_op_i, is_class_op_o;
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assign is_class_op_i = (fpu_req_if.fpu_op == `FPU_CLASS);
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reg [FOP_BITS-1:0] fpu_op;
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reg [`FRM_BITS-1:0] fpu_rnd;
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reg fpu_op_mod;
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reg fflags_en, fflags_en_o;
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always @(*) begin
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fpu_op = fpnew_pkg::SGNJ;
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fpu_rnd = real_frm;
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fpu_op_mod = 0;
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fflags_en = 1;
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fpu_operands[0] = fpu_req_if.rs1_data;
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fpu_operands[1] = fpu_req_if.rs2_data;
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fpu_operands[2] = fpu_req_if.rs3_data;
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case (fpu_req_if.fpu_op)
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`FPU_ADD: begin
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fpu_op = fpnew_pkg::ADD;
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fpu_operands[1] = fpu_req_if.rs1_data;
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fpu_operands[2] = fpu_req_if.rs2_data;
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end
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`FPU_SUB: begin
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fpu_op = fpnew_pkg::ADD;
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fpu_operands[1] = fpu_req_if.rs1_data;
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fpu_operands[2] = fpu_req_if.rs2_data;
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fpu_op_mod = 1;
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end
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`FPU_MUL: fpu_op = fpnew_pkg::MUL;
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`FPU_DIV: fpu_op = fpnew_pkg::DIV;
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`FPU_SQRT: fpu_op = fpnew_pkg::SQRT;
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`FPU_MADD: fpu_op = fpnew_pkg::FMADD;
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`FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end
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`FPU_NMSUB: fpu_op = fpnew_pkg::FNMSUB;
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`FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end
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`FPU_SGNJ: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RNE; fflags_en = 0; end
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`FPU_SGNJN: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RTZ; fflags_en = 0; end
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`FPU_SGNJX: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RDN; fflags_en = 0; end
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`FPU_MIN: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RNE; end
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`FPU_MAX: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RTZ; end
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`FPU_CVTWS: fpu_op = fpnew_pkg::F2I;
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`FPU_CVTWUS:begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = 1; end
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`FPU_CVTSW: fpu_op = fpnew_pkg::I2F;
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`FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end
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`FPU_MVXW: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fflags_en = 0; end
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`FPU_MVWX: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fflags_en = 0; end
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`FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fflags_en = 0; end
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`FPU_CMP: fpu_op = fpnew_pkg::CMP;
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default:;
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endcase
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end
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`DISABLE_TRACING
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fpnew_top #(
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.Features (FPU_FEATURES),
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.Implementation (FPU_IMPLEMENTATION),
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.TagType (logic[`LOG2UP(`FPURQ_SIZE)-1+2:0])
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) fpnew_core (
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.clk_i (clk),
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.rst_ni (1'b1),
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.operands_i (fpu_operands),
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.rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)),
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.op_i (fpnew_pkg::operation_e'(fpu_op)),
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.op_mod_i (fpu_op_mod),
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.src_fmt_i (fpnew_pkg::fp_format_e'(fpu_src_fmt)),
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.dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dst_fmt)),
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.int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)),
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.vectorial_op_i (1'b1),
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.tag_i ({fpu_in_tag, fflags_en, is_class_op_i}),
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.in_valid_i (fpu_in_valid),
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.in_ready_o (fpu_in_ready),
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.flush_i (reset),
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.result_o (fpu_result),
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.status_o (fpu_status),
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.tag_o ({fpu_out_tag, fflags_en_o, is_class_op_o}),
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.out_valid_o (fpu_out_valid),
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.out_ready_i (fpu_out_ready),
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`UNUSED_PIN (busy_o)
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);
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`ENABLE_TRACING
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reg [`NUM_THREADS-1:0][31:0] fpu_result_qual;
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always @(8) begin
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// unpack classify mask result
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if (is_class_op_o) begin
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integer i;
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for (i = 0; i < `NUM_THREADS; i++) begin
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automatic integer l = i / 4;
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automatic integer w = i % 4;
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automatic integer class_mask = fpu_result[l][w * 8 +: 8];
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fpu_result_qual[i][0] = class_mask[7] & class_mask[0];
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fpu_result_qual[i][1] = class_mask[7] & class_mask[1];
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fpu_result_qual[i][2] = class_mask[7] & class_mask[2];
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fpu_result_qual[i][3] = class_mask[7] & class_mask[3];
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fpu_result_qual[i][4] = class_mask[6] & class_mask[3];
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fpu_result_qual[i][5] = class_mask[6] & class_mask[2];
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fpu_result_qual[i][6] = class_mask[6] & class_mask[1];
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fpu_result_qual[i][7] = class_mask[6] & class_mask[0];
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fpu_result_qual[i][8] = class_mask[4];
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fpu_result_qual[i][9] = class_mask[5];
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end
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end else begin
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fpu_result_qual = fpu_result;
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end
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end
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assign fpu_in_valid = fpu_req_if.valid;
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assign fpu_in_tag = fpu_req_if.issue_tag;
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// can accept new request?
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assign fpu_req_if.ready = fpu_in_ready;
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assign fpu_commit_if.valid = fpu_out_valid;
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assign fpu_commit_if.issue_tag = fpu_out_tag;
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assign fpu_commit_if.data = fpu_result_qual;
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assign fpu_commit_if.upd_fflags = fflags_en_o;
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assign fpu_commit_if.fflags_NV = fpu_status.NV;
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assign fpu_commit_if.fflags_DZ = fpu_status.DZ;
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assign fpu_commit_if.fflags_OF = fpu_status.OF;
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assign fpu_commit_if.fflags_UF = fpu_status.UF;
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assign fpu_commit_if.fflags_NX = fpu_status.NX;
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assign fpu_out_ready = fpu_commit_if.ready;
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endmodule |