235 lines
8.5 KiB
Verilog
235 lines
8.5 KiB
Verilog
`include "VX_define.vh"
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module VX_pipeline #(
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parameter CORE_ID = 0
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) (
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`SCOPE_SIGNALS_ISTAGE_IO
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`SCOPE_SIGNALS_LSU_IO
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`SCOPE_SIGNALS_PIPELINE_IO
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`SCOPE_SIGNALS_BE_IO
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// Clock
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input wire clk,
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input wire reset,
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// Dcache core request
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output wire [`NUM_THREADS-1:0] dcache_req_valid,
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output wire [`NUM_THREADS-1:0] dcache_req_rw,
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output wire [`NUM_THREADS-1:0][3:0] dcache_req_byteen,
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output wire [`NUM_THREADS-1:0][29:0] dcache_req_addr,
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output wire [`NUM_THREADS-1:0][31:0] dcache_req_data,
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output wire [`DCORE_TAG_WIDTH-1:0] dcache_req_tag,
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input wire dcache_req_ready,
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// Dcache core reponse
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input wire [`NUM_THREADS-1:0] dcache_rsp_valid,
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input wire [`NUM_THREADS-1:0][31:0] dcache_rsp_data,
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input wire [`DCORE_TAG_WIDTH-1:0] dcache_rsp_tag,
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output wire dcache_rsp_ready,
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// Icache core request
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output wire icache_req_valid,
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output wire icache_req_rw,
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output wire [3:0] icache_req_byteen,
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output wire [29:0] icache_req_addr,
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output wire [31:0] icache_req_data,
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output wire [`ICORE_TAG_WIDTH-1:0] icache_req_tag,
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input wire icache_req_ready,
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// Icache core response
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input wire icache_rsp_valid,
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input wire [31:0] icache_rsp_data,
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input wire [`ICORE_TAG_WIDTH-1:0] icache_rsp_tag,
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output wire icache_rsp_ready,
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// CSR I/O Request
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input wire csr_io_req_valid,
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input wire[11:0] csr_io_req_addr,
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input wire csr_io_req_rw,
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input wire[31:0] csr_io_req_data,
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output wire csr_io_req_ready,
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// CSR I/O Response
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output wire csr_io_rsp_valid,
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output wire[31:0] csr_io_rsp_data,
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input wire csr_io_rsp_ready,
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// Status
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output wire busy,
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output wire ebreak
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);
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// Dcache
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VX_cache_core_req_if #(
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.NUM_REQUESTS(`NUM_THREADS),
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.WORD_SIZE(4),
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.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
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) core_dcache_req_if();
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VX_cache_core_rsp_if #(
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.NUM_REQUESTS(`NUM_THREADS),
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.WORD_SIZE(4),
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.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
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) core_dcache_rsp_if();
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// Icache
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VX_cache_core_req_if #(
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.NUM_REQUESTS(1),
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.WORD_SIZE(4),
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.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
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) core_icache_req_if();
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VX_cache_core_rsp_if #(
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.NUM_REQUESTS(1),
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.WORD_SIZE(4),
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.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
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) core_icache_rsp_if();
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// CSR I/O
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VX_csr_io_req_if csr_io_req_if();
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assign csr_io_req_if.valid = csr_io_req_valid;
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assign csr_io_req_if.rw = csr_io_req_rw;
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assign csr_io_req_if.addr = csr_io_req_addr;
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assign csr_io_req_if.data = csr_io_req_data;
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assign csr_io_req_ready = csr_io_req_if.ready;
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VX_csr_io_rsp_if csr_io_rsp_if();
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assign csr_io_rsp_valid = csr_io_rsp_if.valid;
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assign csr_io_rsp_data = csr_io_rsp_if.data;
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assign csr_io_rsp_if.ready = csr_io_rsp_ready;
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VX_decode_if decode_if();
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VX_execute_if execute_if();
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VX_branch_rsp_if branch_rsp_if();
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VX_warp_ctl_if warp_ctl_if();
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VX_ifetch_rsp_if ifetch_rsp_if();
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VX_wb_if writeback_if();
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VX_wstall_if wstall_if();
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VX_join_if join_if();
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VX_wb_if alu_wb_if();
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VX_wb_if branch_wb_if();
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VX_wb_if lsu_wb_if();
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VX_wb_if csr_wb_if();
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VX_wb_if mul_wb_if();
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wire notify_commit;
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VX_fetch #(
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.CORE_ID(CORE_ID)
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) fetch (
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.clk (clk),
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.reset (reset),
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.icache_req_if (core_icache_req_if),
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.icache_rsp_if (core_icache_rsp_if),
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.wstall_if (wstall_if),
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.join_if (join_if),
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.warp_ctl_if (warp_ctl_if),
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.branch_rsp_if (branch_rsp_if),
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.ifetch_rsp_if (ifetch_rsp_if),
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.busy (busy)
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);
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VX_decode #(
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.CORE_ID(CORE_ID)
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) decode (
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.clk (clk),
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.reset (reset),
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.ifetch_rsp_if (ifetch_rsp_if),
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.decode_if (decode_if),
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.wstall_if (wstall_if),
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.join_if (join_if)
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);
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VX_issue #(
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.CORE_ID(CORE_ID)
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) issue (
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.clk (clk),
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.reset (reset),
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.decode_if (decode_if),
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.writeback_if (writeback_if),
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.execute_if (execute_if),
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`UNUSED_PIN (is_empty)
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);
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VX_execute #(
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.CORE_ID(CORE_ID)
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) execute (
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`SCOPE_SIGNALS_LSU_BIND
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.clk (clk),
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.reset (reset),
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.dcache_req_if (core_dcache_req_if),
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.dcache_rsp_if (core_dcache_rsp_if),
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.csr_io_req_if (csr_io_req_if),
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.csr_io_rsp_if (csr_io_rsp_if),
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.execute_if (execute_if),
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.writeback_if (writeback_if),
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.warp_ctl_if (warp_ctl_if),
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.branch_rsp_if (branch_rsp_if),
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.alu_wb_if (alu_wb_if),
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.branch_wb_if (branch_wb_if),
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.lsu_wb_if (lsu_wb_if),
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.csr_wb_if (csr_wb_if),
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.mul_wb_if (mul_wb_if),
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.notify_commit (notify_commit),
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.ebreak (ebreak)
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);
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VX_writeback #(
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.CORE_ID(CORE_ID)
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) writeback (
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.clk (clk),
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.reset (reset),
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.alu_wb_if (alu_wb_if),
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.branch_wb_if (branch_wb_if),
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.lsu_wb_if (lsu_wb_if),
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.csr_wb_if (csr_wb_if),
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.mul_wb_if (mul_wb_if),
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.writeback_if (writeback_if),
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.notify_commit (notify_commit)
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);
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assign dcache_req_valid = core_dcache_req_if.valid;
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assign dcache_req_rw = core_dcache_req_if.rw;
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assign dcache_req_byteen = core_dcache_req_if.byteen;
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assign dcache_req_addr = core_dcache_req_if.addr;
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assign dcache_req_data = core_dcache_req_if.data;
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assign dcache_req_tag = core_dcache_req_if.tag;
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assign core_dcache_req_if.ready = dcache_req_ready;
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assign core_dcache_rsp_if.valid = dcache_rsp_valid;
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assign core_dcache_rsp_if.data = dcache_rsp_data;
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assign core_dcache_rsp_if.tag = dcache_rsp_tag;
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assign dcache_rsp_ready = core_dcache_rsp_if.ready;
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assign icache_req_valid = core_icache_req_if.valid;
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assign icache_req_rw = core_icache_req_if.rw;
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assign icache_req_byteen = core_icache_req_if.byteen;
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assign icache_req_addr = core_icache_req_if.addr;
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assign icache_req_data = core_icache_req_if.data;
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assign icache_req_tag = core_icache_req_if.tag;
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assign core_icache_req_if.ready = icache_req_ready;
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assign core_icache_rsp_if.valid = icache_rsp_valid;
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assign core_icache_rsp_if.data = icache_rsp_data;
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assign core_icache_rsp_if.tag = icache_rsp_tag;
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assign icache_rsp_ready = core_icache_rsp_if.ready;
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`SCOPE_ASSIGN(scope_busy, busy);
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`SCOPE_ASSIGN(scope_schedule_delay, schedule_delay);
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`SCOPE_ASSIGN(scope_mem_delay, mem_delay);
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`SCOPE_ASSIGN(scope_exec_delay, exec_delay);
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`SCOPE_ASSIGN(scope_gpr_stage_delay, gpr_delay);
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if ((| execute_if.valid) && (~execute_if.alu_ready || ~execute_if.br_ready || ~execute_if.lsu_ready || ~execute_if.csr_ready || ~execute_if.mul_ready || ~execute_if.gpu_ready)) begin
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$display("%t: Core%0d-stall: warp=%0d, PC=%0h, alu=%b, br=%b, lsu=%b, csr=%b, mul=%b, gpu=%b", $time, CORE_ID, execute_if.warp_num, execute_if.curr_PC, ~execute_if.alu_ready, ~execute_if.br_ready, ~execute_if.lsu_ready, ~execute_if.csr_ready, ~execute_if.mul_ready, ~execute_if.gpu_ready);
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end
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end
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`endif
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endmodule
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