55 lines
2.0 KiB
Verilog
55 lines
2.0 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_arb (
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input wire clk,
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input wire reset,
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// inputs
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VX_csr_req_if csr_core_req_if,
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VX_csr_io_req_if csr_io_req_if,
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// output
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VX_csr_req_if csr_req_if,
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// input
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VX_wb_if csr_rsp_if,
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// outputs
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VX_csr_io_rsp_if csr_io_rsp_if,
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VX_wb_if csr_wb_if
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);
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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wire core_select = ~(| csr_io_req_if.valid);
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// requests
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assign csr_req_if.valid = core_select ? csr_core_req_if.valid : {`NUM_THREADS{csr_io_req_if.valid}};
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assign csr_req_if.warp_num = core_select ? csr_core_req_if.warp_num : 0;
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assign csr_req_if.curr_PC = core_select ? csr_core_req_if.curr_PC : 0;
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assign csr_req_if.csr_op = core_select ? csr_core_req_if.csr_op : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS);
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assign csr_req_if.csr_addr = core_select ? csr_core_req_if.csr_addr : csr_io_req_if.addr;
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assign csr_req_if.csr_mask = core_select ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
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assign csr_req_if.rd = core_select ? csr_core_req_if.rd : 0;
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assign csr_req_if.wb = core_select ? csr_core_req_if.wb : 0;
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assign csr_req_if.is_io = ~core_select;
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assign csr_core_req_if.ready = csr_req_if.ready && core_select;
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assign csr_io_req_if.ready = csr_req_if.ready && ~core_select;
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// responses
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assign csr_io_rsp_if.valid = csr_rsp_if.valid[0] & csr_rsp_if.is_io;
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assign csr_io_rsp_if.data = csr_rsp_if.data[0];
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assign csr_wb_if.valid = csr_rsp_if.valid & {`NUM_THREADS{~csr_rsp_if.is_io}};
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assign csr_wb_if.warp_num = csr_rsp_if.warp_num;
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assign csr_wb_if.curr_PC = csr_rsp_if.curr_PC;
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assign csr_wb_if.data = csr_rsp_if.data;
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assign csr_wb_if.rd = csr_rsp_if.rd;
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assign csr_wb_if.wb = csr_rsp_if.wb;
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assign csr_rsp_if.ready = csr_rsp_if.is_io ? csr_io_rsp_if.ready : csr_wb_if.ready;
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endmodule
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