25 lines
696 B
Verilog
25 lines
696 B
Verilog
`include "VX_define.vh"
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module VX_tex_wrap #(
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parameter CORE_ID = 0,
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parameter FRAC_BITS = 20,
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parameter INT_BITS = 32 - FRAC_BITS
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) (
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input wire [`TEX_WRAP_BITS-1:0] wrap_i;
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input wire [31:0] coord_i,
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input wire [31:0] coord_o
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)
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`UNUSED_PARAM (CORE_ID)
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/*always @(*) begin
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case (wrap_i)
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`ALU_AND: msc_result[i] = alu_in1[i] & alu_in2_imm[i];
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`ALU_OR: msc_result[i] = alu_in1[i] | alu_in2_imm[i];
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`ALU_XOR: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i];
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//`ALU_SLL,
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default: msc_result[i] = alu_in1[i] << alu_in2_imm[i][4:0];
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endcase
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end*/
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endmodule |