70 lines
2.4 KiB
Verilog
70 lines
2.4 KiB
Verilog
`include "VX_define.vh"
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module VX_tex_sampler #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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input wire req_valid,
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input wire [`NW_BITS-1:0] req_wid,
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input wire [`NUM_THREADS-1:0] req_tmask,
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input wire [31:0] req_PC,
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input wire [`NR_BITS-1:0] req_rd,
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input wire req_wb,
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input wire [`TEX_FILTER_BITS-1:0] req_filter,
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input wire [`TEX_FORMAT_BITS-1:0] req_format,
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input wire [`NUM_THREADS-1:0][3:0][31:0] req_texels,
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output wire req_ready,
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// ouputs
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output wire rsp_valid,
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output wire [`NW_BITS-1:0] rsp_wid,
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output wire [`NUM_THREADS-1:0] rsp_tmask,
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output wire [31:0] rsp_PC,
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output wire [`NR_BITS-1:0] rsp_rd,
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output wire rsp_wb,
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output wire [`NUM_THREADS-1:0][31:0] rsp_data,
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input wire rsp_ready
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);
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`UNUSED_PARAM (CORE_ID)
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/*
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assign tex_req_if.ready = (& pt_addr_ready);
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assign lsu_req_if.valid = (& pt_addr_valid);
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assign lsu_req_if.wid = tex_req_if.wid;
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assign lsu_req_if.tmask = tex_req_if.tmask;
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assign lsu_req_if.PC = tex_req_if.PC;
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assign lsu_req_if.rd = tex_req_if.rd;
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assign lsu_req_if.wb = tex_req_if.wb;
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assign lsu_req_if.offset = 32'h0000;
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assign lsu_req_if.op_type = `OP_BITS'({1'b0, 3'b000}); //func3 for word load??
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assign lsu_req_if.store_data = {`NUM_THREADS{32'h0000}};
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// wait buffer for fragments / replace with cache/state fragment fifo for bilerp
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// no filtering for point sampling -> directly from dcache to output response
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data}),
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.data_out ({tex_rsp_if.valid, tex_rsp_if.wid, tex_rsp_if.tmask, tex_rsp_if.PC, tex_rsp_if.rd, tex_rsp_if.wb, tex_rsp_if.data})
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);
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// output
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assign stall_out = ~tex_rsp_if.ready && tex_rsp_if.valid;
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// can accept new request?
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assign stall_in = stall_out;
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assign ld_commit_if.ready = ~stall_in;*/
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endmodule |