77 lines
2.0 KiB
Verilog
77 lines
2.0 KiB
Verilog
`include "VX_define.vh"
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module VX_tex_addr_gen #(
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parameter CORE_ID = 0,
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parameter REQ_TAG_WIDTH = 1,
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parameter FRAC_BITS = 20,
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parameter INT_BITS = 32 - FRAC_BITS
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) (
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input wire clk,
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input wire reset,
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// handshake
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input wire valid_in,
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output wire ready_in,
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// inputs
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input wire [`NUM_THREADS-1:0] req_tmask,
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input wire [REQ_TAG_WIDTH-1:0] req_tag,
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input wire [`TEX_FILTER_BITS-1:0] filter,
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input wire [`TEX_WRAP_BITS-1:0] wrap_u,
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input wire [`TEX_WRAP_BITS-1:0] wrap_v,
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input wire [`TEX_ADDR_BITS-1:0] base_addr,
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input wire [`TEX_STRIDE_BITS-1:0] log2_stride,
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input wire [`TEX_WIDTH_BITS-1:0] log2_width,
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input wire [`TEX_HEIGHT_BITS-1:0] log2_height,
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input wire [`NUM_THREADS-1:0][31:0] coord_u,
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input wire [`NUM_THREADS-1:0][31:0] coord_v,
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input wire [`NUM_THREADS-1:0][31:0] lod,
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// outputs
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output wire mem_req_valid,
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output wire [`NUM_THREADS-1:0] mem_req_tmask,
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output wire [`TEX_FILTER_BITS-1:0] mem_req_filter,
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output wire [REQ_TAG_WIDTH-1:0] mem_req_tag,
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output wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr,
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input wire mem_req_ready
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);
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`UNUSED_PARAM (CORE_ID)
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/*`UNUSED_VAR (filter)
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`UNUSED_VAR (lod)
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wire [31:0] u, y;
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wire [31:0] x_offset, y_offset;
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wire [31:0] addr0;
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// addressing mode
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assign x_offset = u >> (5'(FRAC_BITS) - log2_width);
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assign y_offset = v >> (5'(FRAC_BITS) - log2_height);
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assign addr0 = base_addr + (x_offset + (y_offset << log2_width)) << log2_stride;
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wire [3:0] req_valids = 4'(valid_in);
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wire [3:0][31:0] req_address = {4{addr0}};
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VX_pipe_register #(
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.DATAW (1 + 4 + 4 * 32 + REQ_TAG_WIDTH),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({req_valids, req_address, req_tag}),
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.data_out ({mem_req_valid, mem_req_addr, mem_req_tag})
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);
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assign ready_in = ~stall_out;*/
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endmodule |