23 lines
385 B
Systemverilog
23 lines
385 B
Systemverilog
`ifndef VX_CMT_TO_CSR_IF
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`define VX_CMT_TO_CSR_IF
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`include "VX_define.vh"
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interface VX_cmt_to_csr_if ();
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wire valid;
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wire [$clog2(`NUM_THREADS+1)-1:0] commit_size;
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modport master (
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output valid,
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output commit_size
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);
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modport slave (
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input valid,
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input commit_size
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);
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endinterface
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`endif |