44 lines
744 B
Verilog
44 lines
744 B
Verilog
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module VX_warp (
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input wire clk,
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input wire reset,
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input wire stall,
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input wire in_jal,
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input wire[31:0] in_jal_dest,
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input wire in_branch_dir,
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input wire[31:0] in_branch_dest,
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output wire[31:0] out_PC
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);
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reg[31:0] real_PC;
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initial begin
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real_PC = 0;
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end
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var[31:0] temp_PC;
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always @(*) begin
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if (in_jal == 1'b1) begin
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temp_PC = in_jal_dest;
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end else if (in_branch_dir == 1'b1) begin
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temp_PC = in_branch_dest;
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end else begin
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temp_PC = real_PC;
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end
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end
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assign out_PC = temp_PC;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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real_PC <= 0;
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end else if (stall != 1'b1) begin
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real_PC <= temp_PC + 32'h4;
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end
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end
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endmodule |