133 lines
4.3 KiB
Verilog
133 lines
4.3 KiB
Verilog
`include "VX_define.vh"
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module VX_alu_unit (
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input wire clk,
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input wire reset,
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input wire [31:0] src_a,
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input wire [31:0] src_b,
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input wire src_rs2,
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input wire [31:0] itype_immed,
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input wire [19:0] upper_immed,
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input wire [4:0] alu_op,
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input wire [31:0] curr_PC,
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output reg [31:0] alu_result,
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output reg alu_stall
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);
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wire[31:0] div_result_unsigned;
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wire[31:0] div_result_signed;
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wire[31:0] rem_result_unsigned;
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wire[31:0] rem_result_signed;
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wire[63:0] mul_result;
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wire[31:0] alu_in1 = src_a;
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wire[31:0] alu_in2 = (src_rs2 == `RS2_IMMED) ? itype_immed : src_b;
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wire[31:0] upper_immed_s = {upper_immed, {12{1'b0}}};
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reg [7:0] inst_delay;
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reg [7:0] curr_inst_delay;
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always @(*) begin
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case (alu_op)
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`ALU_DIV,
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`ALU_DIVU,
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`ALU_REM,
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`ALU_REMU: inst_delay = `DIV_LATENCY;
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`ALU_MUL,
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`ALU_MULH,
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`ALU_MULHSU,
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`ALU_MULHU: inst_delay = `MUL_LATENCY;
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default: inst_delay = 0;
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endcase
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end
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wire inst_stalled = (curr_inst_delay != inst_delay);
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always @(posedge clk) begin
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if (reset) begin
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curr_inst_delay <= 0;
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end else begin
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curr_inst_delay <= inst_stalled ? (curr_inst_delay + 1) : 0;
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end
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end
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assign alu_stall = inst_stalled;
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always @(*) begin
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case (alu_op)
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`ALU_ADD: alu_result = $signed(alu_in1) + $signed(alu_in2);
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`ALU_SUB: alu_result = $signed(alu_in1) - $signed(alu_in2);
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`ALU_SLLA: alu_result = alu_in1 << alu_in2[4:0];
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`ALU_SLT: alu_result = ($signed(alu_in1) < $signed(alu_in2)) ? 32'h1 : 32'h0;
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`ALU_SLTU: alu_result = alu_in1 < alu_in2 ? 32'h1 : 32'h0;
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`ALU_XOR: alu_result = alu_in1 ^ alu_in2;
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`ALU_SRL: alu_result = alu_in1 >> alu_in2[4:0];
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`ALU_SRA: alu_result = $signed(alu_in1) >>> alu_in2[4:0];
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`ALU_OR: alu_result = alu_in1 | alu_in2;
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`ALU_AND: alu_result = alu_in2 & alu_in1;
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`ALU_SUBU: alu_result = (alu_in1 >= alu_in2) ? 32'h0 : 32'hffffffff;
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`ALU_LUI: alu_result = upper_immed_s;
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`ALU_AUIPC: alu_result = $signed(curr_PC) + $signed(upper_immed_s);
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// TODO: profitable to roll these exceptional cases into inst_delay_tmp to avoid pipeline when possible?
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`ALU_MUL: alu_result = mul_result[31:0];
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`ALU_MULH: alu_result = mul_result[63:32];
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`ALU_MULHSU: alu_result = mul_result[63:32];
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`ALU_MULHU: alu_result = mul_result[63:32];
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`ALU_DIV: alu_result = (alu_in2 == 0) ? 32'hffffffff : div_result_signed;
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`ALU_DIVU: alu_result = (alu_in2 == 0) ? 32'hffffffff : div_result_unsigned;
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`ALU_REM: alu_result = (alu_in2 == 0) ? alu_in1 : rem_result_signed;
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`ALU_REMU: alu_result = (alu_in2 == 0) ? alu_in1 : rem_result_unsigned;
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default: alu_result = 32'h0;
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endcase // alu_op
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end
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VX_divide #(
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.WIDTHN(32),
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.WIDTHD(32),
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.NSIGNED(0),
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.DSIGNED(0),
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.PIPELINE(`DIV_LATENCY)
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) udiv (
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.clk(clk),
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.reset(reset),
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.numer(alu_in1),
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.denom(alu_in2),
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.quotient(div_result_unsigned),
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.remainder(rem_result_unsigned)
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);
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VX_divide #(
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.WIDTHN(32),
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.WIDTHD(32),
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.NSIGNED(1),
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.DSIGNED(1),
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.PIPELINE(`DIV_LATENCY)
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) sdiv (
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.clk(clk),
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.reset(reset),
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.numer(alu_in1),
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.denom(alu_in2),
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.quotient(div_result_signed),
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.remainder(rem_result_signed)
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);
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wire [32:0] mul_dataa = {(alu_op == `ALU_MULHU) ? 1'b0 : alu_in1[31], alu_in1};
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wire [32:0] mul_datab = {(alu_op == `ALU_MULHU || alu_op == `ALU_MULHSU) ? 1'b0 : alu_in2[31], alu_in2};
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VX_mult #(
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.WIDTHA(33),
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.WIDTHB(33),
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.WIDTHP(64),
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.SIGNED(1),
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.PIPELINE(`MUL_LATENCY)
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) multiplier (
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.clk(clk),
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.reset(reset),
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.dataa(mul_dataa),
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.datab(mul_datab),
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.result(mul_result)
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);
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endmodule |