270 lines
9.6 KiB
Verilog
270 lines
9.6 KiB
Verilog
`include "VX_define.vh"
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`include "VX_cache_config.vh"
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module Vortex
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#(
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parameter CORE_ID = 0
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) (
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`ifdef SINGLE_CORE_BENCH
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// Clock
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input wire clk,
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input wire reset,
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// IO
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output wire io_valid,
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output wire [31:0] io_data,
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// DRAM Dcache Req
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output wire dram_req_read,
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output wire dram_req_write,
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output wire [31:0] dram_req_addr,
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output wire [`DBANK_LINE_SIZE-1:0] dram_req_data,
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input wire dram_req_full,
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// DRAM Dcache Rsp
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input wire dram_rsp_valid,
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input wire [31:0] dram_rsp_addr,
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input wire [`DBANK_LINE_SIZE-1:0] dram_rsp_data,
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output wire dram_rsp_ready,
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// DRAM Icache Req
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output wire I_dram_req_read,
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output wire I_dram_req_write,
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output wire [31:0] I_dram_req_addr,
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output wire [`IBANK_LINE_SIZE-1:0] I_dram_req_data,
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input wire I_dram_req_full,
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// DRAM Icache Rsp
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input wire I_dram_rsp_valid,
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input wire [31:0] I_dram_rsp_addr,
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input wire [`IBANK_LINE_SIZE-1:0] I_dram_rsp_data,
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output wire I_dram_rsp_ready,
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// LLC Snooping
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input wire snp_req_valid,
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input wire [31:0] snp_req_addr,
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output wire snp_req_full,
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output wire out_ebreak
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`else
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input wire clk,
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input wire reset,
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// IO
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output wire io_valid,
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output wire[31:0] io_data,
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// DRAM Dcache Req
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output wire dram_req_read,
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output wire dram_req_write,
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output wire [31:0] dram_req_addr,
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output wire [`DBANK_LINE_SIZE-1:0] dram_req_data,
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input wire dram_req_full,
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// DRAM Dcache Rsp
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input wire dram_rsp_valid,
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input wire [31:0] dram_rsp_addr,
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input wire [`DBANK_LINE_SIZE-1:0] dram_rsp_data,
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output wire dram_rsp_ready,
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// DRAM Icache Req
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output wire I_dram_req_read,
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output wire I_dram_req_write,
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output wire [31:0] I_dram_req_addr,
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output wire [`IBANK_LINE_SIZE-1:0] I_dram_req_data,
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input wire I_dram_req_full,
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// DRAM Icache Rsp
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output wire I_dram_rsp_ready,
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input wire I_dram_rsp_valid,
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input wire [31:0] I_dram_rsp_addr,
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input wire [`IBANK_LINE_SIZE-1:0] I_dram_rsp_data,
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input wire snp_req_valid,
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input wire [31:0] snp_req_addr,
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output wire snp_req_full,
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output wire out_ebreak
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`endif
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);
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`DEBUG_BEGIN
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wire scheduler_empty;
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`DEBUG_END
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wire memory_delay;
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wire exec_delay;
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wire gpr_stage_delay;
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wire schedule_delay;
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// Dcache Interface
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VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp();
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VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req();
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VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_qual();
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VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_req();
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VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_res();
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assign vx_gpu_dcache_dram_res.dram_rsp_valid = dram_rsp_valid;
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assign vx_gpu_dcache_dram_res.dram_rsp_addr = dram_rsp_addr;
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assign dram_req_write = vx_gpu_dcache_dram_req.dram_req_write;
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assign dram_req_read = vx_gpu_dcache_dram_req.dram_req_read;
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assign dram_req_addr = vx_gpu_dcache_dram_req.dram_req_addr;
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assign dram_rsp_ready = vx_gpu_dcache_dram_req.dram_rsp_ready;
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assign vx_gpu_dcache_dram_req.dram_req_full = dram_req_full;
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genvar i;
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generate
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for (i = 0; i < `DBANK_LINE_WORDS; i=i+1) begin
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assign vx_gpu_dcache_dram_res.dram_rsp_data[i] = dram_rsp_data[i * 32 +: 32];
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assign dram_req_data[i * 32 +: 32] = vx_gpu_dcache_dram_req.dram_req_data[i];
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end
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endgenerate
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wire temp_io_valid = (!memory_delay)
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&& (|vx_dcache_req.core_req_valid)
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&& (vx_dcache_req.core_req_mem_write[0] != `NO_MEM_WRITE)
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&& (vx_dcache_req.core_req_addr[0] == 32'h00010000);
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wire[31:0] temp_io_data = vx_dcache_req.core_req_writedata[0];
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assign io_valid = temp_io_valid;
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assign io_data = temp_io_data;
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assign vx_dcache_req_qual.core_req_valid = vx_dcache_req.core_req_valid & {`NUM_THREADS{~io_valid}};
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assign vx_dcache_req_qual.core_req_addr = vx_dcache_req.core_req_addr;
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assign vx_dcache_req_qual.core_req_writedata = vx_dcache_req.core_req_writedata;
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assign vx_dcache_req_qual.core_req_mem_read = vx_dcache_req.core_req_mem_read;
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assign vx_dcache_req_qual.core_req_mem_write = vx_dcache_req.core_req_mem_write;
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assign vx_dcache_req_qual.core_req_rd = vx_dcache_req.core_req_rd;
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assign vx_dcache_req_qual.core_req_wb = vx_dcache_req.core_req_wb;
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assign vx_dcache_req_qual.core_req_warp_num = vx_dcache_req.core_req_warp_num;
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assign vx_dcache_req_qual.core_req_pc = vx_dcache_req.core_req_pc;
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assign vx_dcache_req_qual.core_no_wb_slot = vx_dcache_req.core_no_wb_slot;
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VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_rsp();
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VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_req();
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VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_req();
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VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_res();
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assign vx_gpu_icache_dram_res.dram_rsp_valid = I_dram_rsp_valid;
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assign vx_gpu_icache_dram_res.dram_rsp_addr = I_dram_rsp_addr;
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assign I_dram_req_write = vx_gpu_icache_dram_req.dram_req_write;
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assign I_dram_req_read = vx_gpu_icache_dram_req.dram_req_read;
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assign I_dram_req_addr = vx_gpu_icache_dram_req.dram_req_addr;
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assign I_dram_rsp_ready = vx_gpu_icache_dram_req.dram_rsp_ready;
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assign vx_gpu_icache_dram_req.dram_req_full = I_dram_req_full;
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genvar j;
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generate
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for (j = 0; j < `IBANK_LINE_WORDS; j = j + 1) begin
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assign vx_gpu_icache_dram_res.dram_rsp_data[j] = I_dram_rsp_data[j * 32 +: 32];
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assign I_dram_req_data[j * 32 +: 32] = vx_gpu_icache_dram_req.dram_req_data[j];
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end
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endgenerate
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/////////////////////////////////////////////////////////////////////////
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// Front-end to Back-end
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VX_frE_to_bckE_req_inter vx_bckE_req(); // New instruction request to EXE/MEM
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// Back-end to Front-end
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VX_wb_inter vx_writeback_inter(); // Writeback to GPRs
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VX_branch_response_inter vx_branch_rsp(); // Branch Resolution to Fetch
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VX_jal_response_inter vx_jal_rsp(); // Jump resolution to Fetch
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// CSR Buses
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// VX_csr_write_request_inter vx_csr_w_req();
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VX_warp_ctl_inter vx_warp_ctl();
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VX_gpu_snp_req_rsp vx_gpu_icache_snp_req();
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VX_gpu_snp_req_rsp vx_gpu_dcache_snp_req();
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assign vx_gpu_dcache_snp_req.snp_req_valid = snp_req_valid;
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assign vx_gpu_dcache_snp_req.snp_req_addr = snp_req_addr;
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assign snp_req_full = vx_gpu_dcache_snp_req.snp_req_full;
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VX_front_end vx_front_end(
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.clk (clk),
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.reset (reset),
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.vx_warp_ctl (vx_warp_ctl),
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.vx_bckE_req (vx_bckE_req),
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.schedule_delay (schedule_delay),
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.vx_icache_rsp (vx_icache_rsp),
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.vx_icache_req (vx_icache_req),
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.vx_jal_rsp (vx_jal_rsp),
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.vx_branch_rsp (vx_branch_rsp),
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.fetch_ebreak (out_ebreak)
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);
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VX_scheduler schedule(
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.clk (clk),
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.reset (reset),
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.memory_delay (memory_delay),
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.exec_delay (exec_delay),
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.gpr_stage_delay (gpr_stage_delay),
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.vx_bckE_req (vx_bckE_req),
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.vx_writeback_inter (vx_writeback_inter),
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.schedule_delay (schedule_delay),
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.is_empty (scheduler_empty)
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);
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VX_back_end #(.CORE_ID(CORE_ID)) vx_back_end(
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.clk (clk),
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.reset (reset),
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.schedule_delay (schedule_delay),
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.vx_warp_ctl (vx_warp_ctl),
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.vx_bckE_req (vx_bckE_req),
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.vx_jal_rsp (vx_jal_rsp),
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.vx_branch_rsp (vx_branch_rsp),
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.vx_dcache_rsp (vx_dcache_rsp),
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.vx_dcache_req (vx_dcache_req),
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.vx_writeback_inter (vx_writeback_inter),
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.out_mem_delay (memory_delay),
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.out_exec_delay (exec_delay),
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.gpr_stage_delay (gpr_stage_delay)
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);
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VX_dmem_controller vx_dmem_controller(
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.clk (clk),
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.reset (reset),
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// Dram <-> Dcache
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.vx_gpu_dcache_dram_req (vx_gpu_dcache_dram_req),
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.vx_gpu_dcache_dram_res (vx_gpu_dcache_dram_res),
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.vx_gpu_dcache_snp_req (vx_gpu_dcache_snp_req),
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// Dram <-> Icache
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.vx_gpu_icache_dram_req (vx_gpu_icache_dram_req),
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.vx_gpu_icache_dram_res (vx_gpu_icache_dram_res),
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.vx_gpu_icache_snp_req (vx_gpu_icache_snp_req),
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// Core <-> Icache
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.vx_icache_req (vx_icache_req),
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.vx_icache_rsp (vx_icache_rsp),
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// Core <-> Dcache
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.vx_dcache_req (vx_dcache_req_qual),
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.vx_dcache_rsp (vx_dcache_rsp)
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);
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// VX_csr_handler vx_csr_handler(
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// .clk (clk),
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// .in_decode_csr_address(decode_csr_address),
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// .vx_csr_w_req (vx_csr_w_req),
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// .in_wb_valid (vx_writeback_inter.wb_valid[0]),
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// .out_decode_csr_data (csr_decode_csr_data)
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// );
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endmodule // Vortex
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