133 lines
3.4 KiB
Verilog
133 lines
3.4 KiB
Verilog
`include "VX_define.vh"
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module VX_back_end
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#(
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parameter CORE_ID = 0
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)
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(
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input wire clk,
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input wire reset,
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input wire schedule_delay,
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VX_gpu_dcache_rsp_inter vx_dcache_rsp,
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VX_gpu_dcache_req_inter vx_dcache_req,
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output wire out_mem_delay,
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output wire out_exec_delay,
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output wire gpr_stage_delay,
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VX_jal_response_inter vx_jal_rsp,
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VX_branch_response_inter vx_branch_rsp,
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VX_frE_to_bckE_req_inter vx_bckE_req,
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VX_wb_inter vx_writeback_inter,
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VX_warp_ctl_inter vx_warp_ctl
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);
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VX_wb_inter vx_writeback_temp();
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assign vx_writeback_inter.wb = vx_writeback_temp.wb;
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assign vx_writeback_inter.rd = vx_writeback_temp.rd;
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assign vx_writeback_inter.write_data = vx_writeback_temp.write_data;
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assign vx_writeback_inter.wb_valid = vx_writeback_temp.wb_valid;
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assign vx_writeback_inter.wb_warp_num = vx_writeback_temp.wb_warp_num;
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assign vx_writeback_inter.wb_pc = vx_writeback_temp.wb_pc;
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// assign VX_writeback_inter(vx_writeback_temp);
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wire no_slot_mem;
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wire no_slot_exec;
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// LSU input + output
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VX_lsu_req_inter vx_lsu_req();
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VX_inst_mem_wb_inter vx_mem_wb();
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// Exec unit input + output
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VX_exec_unit_req_inter vx_exec_unit_req();
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VX_inst_exec_wb_inter vx_inst_exec_wb();
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// GPU unit input
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VX_gpu_inst_req_inter vx_gpu_inst_req();
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// CSR unit inputs
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VX_csr_req_inter vx_csr_req();
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VX_csr_wb_inter vx_csr_wb();
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wire no_slot_csr;
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wire stall_gpr_csr;
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VX_gpr_stage vx_gpr_stage(
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.clk (clk),
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.reset (reset),
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.schedule_delay (schedule_delay),
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.vx_writeback_inter(vx_writeback_temp),
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.vx_bckE_req (vx_bckE_req),
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// New
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.vx_exec_unit_req(vx_exec_unit_req),
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.vx_lsu_req (vx_lsu_req),
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.vx_gpu_inst_req (vx_gpu_inst_req),
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.vx_csr_req (vx_csr_req),
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.stall_gpr_csr (stall_gpr_csr),
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// End new
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.memory_delay (out_mem_delay),
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.exec_delay (out_exec_delay),
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.gpr_stage_delay (gpr_stage_delay)
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);
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VX_lsu load_store_unit (
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.clk (clk),
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.reset (reset),
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.vx_lsu_req (vx_lsu_req),
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.vx_mem_wb (vx_mem_wb),
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.vx_dcache_rsp(vx_dcache_rsp),
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.vx_dcache_req(vx_dcache_req),
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.out_delay (out_mem_delay),
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.no_slot_mem (no_slot_mem)
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);
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VX_execute_unit vx_execUnit (
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.clk (clk),
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.reset (reset),
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.vx_exec_unit_req(vx_exec_unit_req),
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.vx_inst_exec_wb (vx_inst_exec_wb),
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.vx_jal_rsp (vx_jal_rsp),
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.vx_branch_rsp (vx_branch_rsp),
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.out_delay (out_exec_delay),
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.no_slot_exec (no_slot_exec)
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);
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VX_gpgpu_inst vx_gpgpu_inst (
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.vx_gpu_inst_req(vx_gpu_inst_req),
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.vx_warp_ctl (vx_warp_ctl)
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);
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// VX_csr_wrapper vx_csr_wrapper(
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// .vx_csr_req(vx_csr_req),
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// .vx_csr_wb (vx_csr_wb)
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// );
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VX_csr_pipe #(
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.CORE_ID(CORE_ID)
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) vx_csr_pipe (
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.clk (clk),
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.reset (reset),
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.no_slot_csr (no_slot_csr),
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.vx_csr_req (vx_csr_req),
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.vx_writeback(vx_writeback_temp),
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.vx_csr_wb (vx_csr_wb),
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.stall_gpr_csr(stall_gpr_csr)
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);
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VX_writeback vx_wb (
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.clk (clk),
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.reset (reset),
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.vx_mem_wb (vx_mem_wb),
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.vx_inst_exec_wb (vx_inst_exec_wb),
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.vx_csr_wb (vx_csr_wb),
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.vx_writeback_inter(vx_writeback_temp),
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.no_slot_mem (no_slot_mem),
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.no_slot_exec (no_slot_exec),
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.no_slot_csr (no_slot_csr)
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);
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endmodule |