49 lines
1.3 KiB
Verilog
49 lines
1.3 KiB
Verilog
`include "VX_tex_define.vh"
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/*
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switch(addressing_mode) {
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case undefined: return is_undefined;
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case clamp_to_edge: return intdowni(max(0, min(coord, coorddim - 1)));
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case clamp_to_border: return is_border;
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case repeat:
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tile = intdowni(coord / coorddim);
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return intdowni(coord - (tile * coorddim));
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case mirrored_repeat:
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mirrored_coord = (coord < 0) ? (-coord - 1) : coord;
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tile = intdowni(mirrored_coord / coorddim);
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mirrored_coord = intdowni(mirrored_coord - (tile * coorddim));
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if (tile & 1) {
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mirrored_coord = (coorddim - 1) - mirrored_coord;
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}
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return mirrored_coord;
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}
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*/
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module VX_tex_wrap #(
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parameter CORE_ID = 0
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) (
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input wire [`TEX_WRAP_BITS-1:0] wrap_i,
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input wire [31:0] coord_i,
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input wire [`FIXED_FRAC-1:0] coord_o
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);
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`UNUSED_PARAM (CORE_ID)
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reg [31:0] coord_r;
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wire [31:0] clamp = `CLAMP(coord_i, 0, `FIXED_MASK);
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always @(*) begin
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case (wrap_i)
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`TEX_WRAP_CLAMP:
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coord_r = clamp[`FIXED_FRAC-1:0];
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`TEX_WRAP_MIRROR:
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coord_r = coord_i[`FIXED_FRAC-1:0] ^ {`FIXED_FRAC{coord_i[`FIXED_FRAC]}};
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default: //`TEX_WRAP_REPEAT
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coord_r = coord_i[`FIXED_FRAC-1:0];
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endcase
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end
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assign coord_o = coord_r;
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endmodule |