91 lines
2.8 KiB
Verilog
91 lines
2.8 KiB
Verilog
`include "VX_tex_define.vh"
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module VX_tex_sampler #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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input wire req_valid,
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input wire [`NW_BITS-1:0] req_wid,
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input wire [`NUM_THREADS-1:0] req_tmask,
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input wire [31:0] req_PC,
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input wire [`NR_BITS-1:0] req_rd,
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input wire req_wb,
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input wire [`TEX_FILTER_BITS-1:0] req_filter,
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input wire [`TEX_FORMAT_BITS-1:0] req_format,
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input wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] req_u,
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input wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] req_v,
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input wire [`NUM_THREADS-1:0][3:0][31:0] req_texels,
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output wire req_ready,
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// ouputs
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output wire rsp_valid,
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output wire [`NW_BITS-1:0] rsp_wid,
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output wire [`NUM_THREADS-1:0] rsp_tmask,
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output wire [31:0] rsp_PC,
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output wire [`NR_BITS-1:0] rsp_rd,
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output wire rsp_wb,
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output wire [`NUM_THREADS-1:0][31:0] rsp_data,
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input wire rsp_ready
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);
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`UNUSED_PARAM (CORE_ID)
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wire [`NUM_THREADS-1:0][31:0] req_data;
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wire [`NUM_THREADS-1:0][31:0] req_data_bilerp;
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wire stall_out;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [3:0][63:0] formatted_data;
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wire [`NUM_COLOR_CHANNEL-1:0] color_enable;
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VX_tex_format #(
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.CORE_ID (CORE_ID),
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.NUM_TEXELS (4)
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) tex_format (
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.texel_data (req_texels[i]),
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.format (req_format),
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.color_enable (color_enable),
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.formatted_texel(formatted_data)
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);
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VX_tex_bilerp #(
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.CORE_ID (CORE_ID)
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) tex_bilerp (
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.blendU (req_u[i][`BLEND_FRAC_64-1:0]),
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.blendV (req_v[i][`BLEND_FRAC_64-1:0]),
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.color_enable (color_enable),
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.texels (formatted_data),
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.sampled_data (req_data_bilerp[i])
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);
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign req_data[i] = (req_filter == `TEX_FILTER_BITS'(0)) ? req_texels[i][0] : req_data_bilerp[i];
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end
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assign stall_out = rsp_valid && ~rsp_ready;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, req_data}),
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.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data})
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);
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// can accept new request?
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assign req_ready = ~stall_out;
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endmodule |