c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
109 lines
3.1 KiB
Systemverilog
109 lines
3.1 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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module VX_ipdom_stack #(
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parameter WIDTH = 1,
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parameter DEPTH = 1,
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parameter OUT_REG = 0,
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parameter ADDRW = `LOG2UP(DEPTH)
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) (
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input wire clk,
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input wire reset,
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input wire [WIDTH-1:0] q0,
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input wire [WIDTH-1:0] q1,
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output wire [WIDTH-1:0] d,
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output wire d_set,
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input wire push,
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input wire pop,
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output wire empty,
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output wire full
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);
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reg slot_set [DEPTH-1:0];
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reg [ADDRW-1:0] rd_ptr, wr_ptr;
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reg empty_r, full_r;
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wire [WIDTH-1:0] d0, d1;
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wire d_set_n = slot_set[rd_ptr];
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always @(posedge clk) begin
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if (reset) begin
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rd_ptr <= '0;
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wr_ptr <= '0;
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empty_r <= 1;
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full_r <= 0;
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end else begin
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`ASSERT(~push || ~full, ("runtime error: writing to a full stack!"));
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`ASSERT(~pop || ~empty, ("runtime error: reading an empty stack!"));
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`ASSERT(~push || ~pop, ("runtime error: push and pop in same cycle not supported!"));
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if (push) begin
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rd_ptr <= wr_ptr;
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wr_ptr <= wr_ptr + ADDRW'(1);
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empty_r <= 0;
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full_r <= (ADDRW'(DEPTH-1) == wr_ptr);
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end else if (pop) begin
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wr_ptr <= wr_ptr - ADDRW'(d_set_n);
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rd_ptr <= rd_ptr - ADDRW'(d_set_n);
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empty_r <= (rd_ptr == 0) && (d_set_n == 1);
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full_r <= 0;
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end
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end
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end
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VX_dp_ram #(
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.DATAW (WIDTH * 2),
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.SIZE (DEPTH),
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.OUT_REG (OUT_REG ? 1 : 0),
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.LUTRAM (OUT_REG ? 0 : 1)
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) store (
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.clk (clk),
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.read (1'b1),
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.write (push),
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`UNUSED_PIN (wren),
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.waddr (wr_ptr),
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.wdata ({q1, q0}),
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.raddr (rd_ptr),
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.rdata ({d1, d0})
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);
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always @(posedge clk) begin
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if (push) begin
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slot_set[wr_ptr] <= 0;
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end else if (pop) begin
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slot_set[rd_ptr] <= 1;
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end
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end
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wire d_set_r;
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VX_pipe_register #(
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.DATAW (1),
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.DEPTH (OUT_REG)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (1'b1),
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.data_in (d_set_n),
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.data_out (d_set_r)
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);
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assign d = d_set_r ? d0 : d1;
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assign d_set = ~d_set_r;
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assign empty = empty_r;
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assign full = full_r;
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endmodule
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