17 lines
294 B
Verilog
17 lines
294 B
Verilog
`ifndef VX_PERF_MEMSYS_IF
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`define VX_PERF_MEMSYS_IF
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`include "VX_define.vh"
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interface VX_perf_memsys_if ();
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VX_perf_cache_if dcache_if;
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VX_perf_cache_if icache_if;
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wire [63:0] dram_latency;
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wire [63:0] dram_requests;
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wire [63:0] dram_responses;
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endinterface
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`endif |