758 lines
66 KiB
Plaintext
758 lines
66 KiB
Plaintext
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Design Compiler Graphical
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DC Ultra (TM)
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DFTMAX (TM)
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Power Compiler (TM)
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DesignWare (R)
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DC Expert (TM)
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Design Vision (TM)
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HDL Compiler (TM)
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VHDL Compiler (TM)
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DFT Compiler
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Design Compiler(R)
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Version O-2018.06-SP3 for linux64 - Oct 18, 2018
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Copyright (c) 1988 - 2018 Synopsys, Inc.
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This software and the associated documentation are proprietary to Synopsys,
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Inc. This software may only be used in accordance with the terms and conditions
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of a written license agreement with Synopsys, Inc. All other use, reproduction,
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or distribution of this software is strictly prohibited.
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Initializing...
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set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db]
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/nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db
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set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db dw_foundation.sldb]
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* sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db dw_foundation.sldb
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set symbol_library {}
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set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db]
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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db
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set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v ]
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VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v
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# set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v # ]
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set top_level Vortex
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Vortex
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analyze -format sverilog $verilog_files
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Running PRESTO HDLC
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Compiling source file ../rtl/VX_countones.v
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Compiling source file ../rtl/VX_priority_encoder_w_mask.v
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Compiling source file ../rtl/interfaces/VX_dram_req_rsp_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_dram_req_rsp_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/cache/VX_Cache_Bank.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Compiling source file ../rtl/cache/VX_cache_data.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Compiling source file ../rtl/cache/VX_d_cache.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Warning: ../rtl/cache/VX_d_cache.v:50: Parameter keyword used in local parameter declaration. (VER-329)
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Compiling source file ../rtl/shared_memory/VX_bank_valids.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Compiling source file ../rtl/shared_memory/VX_priority_encoder_sm.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Compiling source file ../rtl/shared_memory/VX_shared_memory.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Compiling source file ../rtl/shared_memory/VX_shared_memory_block.v
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Compiling source file ../rtl/VX_dmem_controller.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/VX_generic_priority_encoder.v
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Compiling source file ../rtl/VX_generic_stack.v
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Compiling source file ../rtl/interfaces/VX_join_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_join_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/VX_csr_wrapper.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/interfaces/VX_csr_req_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_csr_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_csr_wb_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_csr_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/VX_gpgpu_inst.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/interfaces/VX_gpu_inst_req_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_gpu_inst_req_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_wstall_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_wstall_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_inst_exec_wb_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_inst_exec_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/VX_lsu.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/VX_execute_unit.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/VX_lsu_addr_gen.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/VX_inst_multiplex.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/interfaces/VX_exec_unit_req_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_exec_unit_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_lsu_req_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_lsu_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/VX_alu.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/VX_back_end.v
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Compiling source file ../rtl/VX_gpr_stage.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/interfaces/VX_gpr_data_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_gpr_data_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/VX_csr_handler.v
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Compiling source file ../rtl/VX_decode.v
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Opening include file ../rtl//VX_define.v
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Warning: ../rtl/VX_csr_handler.v:34: The statements in initial blocks are ignored. (VER-281)
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Compiling source file ../rtl/VX_define.v
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Compiling source file ../rtl/VX_scheduler.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/VX_fetch.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/VX_front_end.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/VX_generic_register.v
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Compiling source file ../rtl/VX_gpr.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/VX_gpr_wrapper.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/VX_priority_encoder.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/VX_warp_scheduler.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/VX_writeback.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/byte_enabled_simple_dual_port_ram.v
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Opening include file ../rtl//VX_define.v
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Compiling source file ../rtl/interfaces/VX_branch_response_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_branch_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_dcache_request_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_dcache_request_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_dcache_response_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_dcache_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_frE_to_bckE_req_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_frE_to_bckE_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_gpr_clone_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_gpr_clone_inter.v:9: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_gpr_jal_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_gpr_jal_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_gpr_read_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_gpr_read_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_gpr_wspawn_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_gpr_wspawn_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_icache_request_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_icache_request_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_icache_response_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_icache_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_inst_mem_wb_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_inst_mem_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_inst_meta_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_inst_meta_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_jal_response_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_jal_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_mem_req_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_mem_req_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_mw_wb_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_mw_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_warp_ctl_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_warp_ctl_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/interfaces/VX_wb_inter.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Information: ../rtl/interfaces/VX_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
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Compiling source file ../rtl/pipe_regs/VX_d_e_reg.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Compiling source file ../rtl/pipe_regs/VX_f_d_reg.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Compiling source file ../rtl/Vortex.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Compiling source file ../rtl/cache/VX_cache_bank_valid.v
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Opening include file ../rtl/interfaces/../VX_define.v
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Presto compilation completed successfully.
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Loading db file '/nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db'
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Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db'
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Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db'
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Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db'
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Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db'
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Loading db file '/tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/dw_foundation.sldb'
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1
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elaborate Vortex
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Loading db file '/tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/gtech.db'
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Loading db file '/tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/standard.sldb'
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Loading link library 'sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c'
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Loading link library 'USERLIB_ss_0p81v_0p81v_m40c'
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Loading link library 'USERLIB_ss_0p81v_0p81v_m40c'
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Loading link library 'USERLIB_ss_0p81v_0p81v_m40c'
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Loading link library 'USERLIB_ss_0p81v_0p81v_m40c'
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Loading link library 'gtech'
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Running PRESTO HDLC
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Presto compilation completed successfully.
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Elaborated 1 design.
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Current design is now 'Vortex'.
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Information: Building the design 'VX_front_end' instantiated from design 'Vortex' with
|
|
the parameters "|((N%clk%)(N%reset%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%schedule_delay%)(N%icache_response_fe%I%WORK/VX_icache_response_inter%%)(N%icache_request_fe%I%WORK/VX_icache_request_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%fetch_ebreak%))". (HDL-193)
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Presto compilation completed successfully.
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|
Warning: Filename too long >255 chars. Renaming file:
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|
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_FRONT_END_I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_ICACHE_RESPONSE_FE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_FE_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__.mr'
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to
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|
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_FRONT_END_I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_ICACHE_RESPONSE_FE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_FE_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_35FE527370C98E3C09E2E6E2555D7EE6F02ECB4FA9775364_000.mr'
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Information: Building the design 'VX_scheduler' instantiated from design 'Vortex' with
|
|
the parameters "|((N%clk%)(N%reset%)(N%memory_delay%)(N%gpr_stage_delay%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%schedule_delay%))". (HDL-193)
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|
|
Inferred memory devices in process
|
|
in routine VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__ line 46 in file
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'../rtl/VX_scheduler.v'.
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===============================================================================
|
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| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
|
===============================================================================
|
|
| rename_table_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N |
|
|
===============================================================================
|
|
Statistics for MUX_OPs
|
|
================================================================================================================================
|
|
| block name/line | Inputs | Outputs | # sel inputs |
|
|
================================================================================================================================
|
|
| VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__/28 | 32 | 1 | 5 |
|
|
| VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__/29 | 32 | 1 | 5 |
|
|
================================================================================================================================
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Presto compilation completed successfully.
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|
Information: Building the design 'VX_back_end' instantiated from design 'Vortex' with
|
|
the parameters "|((N%clk%)(N%reset%)(N%schedule_delay%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%out_mem_delay%)(N%gpr_stage_delay%))". (HDL-193)
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|
Presto compilation completed successfully.
|
|
Warning: Filename too long >255 chars. Renaming file:
|
|
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_BACK_END_I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__I_VX_WRITEBACK_INTER_VX_WB_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_VX_DCACHE_RSP_VX_DCACHE_RESPONSE_INTER__I_VX_DCACHE_REQ_VX_DCACHE_REQUEST_INTER__.mr'
|
|
to
|
|
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_BACK_END_I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__I_VX_WRITEBACK_INTER_VX_WB_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__I__B458045CB598257C352A6473E41AFB0017DAE536C3121AF6_000.mr'
|
|
Information: Building the design 'VX_dmem_controller' instantiated from design 'Vortex' with
|
|
the parameters "|((N%clk%)(N%reset%)(N%VX_dram_req_rsp%I%WORK/VX_dram_req_rsp_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%))". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_fetch' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
|
|
the parameters "|((N%clk%)(N%reset%)(N%VX_wstall%I%WORK/VX_wstall_inter%%)(N%VX_join%I%WORK/VX_join_inter%%)(N%schedule_delay%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%icache_response%I%WORK/VX_icache_response_inter%%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%icache_request%I%WORK/VX_icache_request_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%out_ebreak%)(N%fe_inst_meta_fd%I%WORK/VX_inst_meta_inter%%))". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Warning: Filename too long >255 chars. Renaming file:
|
|
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_FETCH_I_VX_WSTALL_VX_WSTALL_INTER__I_VX_JOIN_VX_JOIN_INTER__I_ICACHE_RESPONSE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_FE_INST_META_FD_VX_INST_META_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__.mr'
|
|
to
|
|
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_FETCH_I_VX_WSTALL_VX_WSTALL_INTER__I_VX_JOIN_VX_JOIN_INTER__I_ICACHE_RESPONSE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RS_86A42238AAF2AFE24C53E826055B694A355B7E541802DCF6_000.mr'
|
|
Information: Building the design 'VX_f_d_reg' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
|
|
the parameters "|((N%clk%)(N%reset%)(N%in_freeze%)(N%fe_inst_meta_fd%I%WORK/VX_inst_meta_inter%%)(N%fd_inst_meta_de%I%WORK/VX_inst_meta_inter%%))". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_decode' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
|
|
the parameters "|((N%fd_inst_meta_de%I%WORK/VX_inst_meta_inter%%)(N%VX_frE_to_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_wstall%I%WORK/VX_wstall_inter%%)(N%VX_join%I%WORK/VX_join_inter%%))". (HDL-193)
|
|
Warning: ../rtl/VX_decode.v:152: signed to unsigned assignment occurs. (VER-318)
|
|
Warning: ../rtl/VX_decode.v:300: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
|
|
Warning: ../rtl/VX_decode.v:315: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
|
|
|
|
Statistics for case statements in always block at line 159 in file
|
|
'../rtl/VX_decode.v'
|
|
===============================================
|
|
| Line | full/ parallel |
|
|
===============================================
|
|
| 160 | auto/auto |
|
|
===============================================
|
|
|
|
Statistics for case statements in always block at line 190 in file
|
|
'../rtl/VX_decode.v'
|
|
===============================================
|
|
| Line | full/ parallel |
|
|
===============================================
|
|
| 191 | auto/auto |
|
|
===============================================
|
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|
|
Statistics for case statements in always block at line 244 in file
|
|
'../rtl/VX_decode.v'
|
|
===============================================
|
|
| Line | full/ parallel |
|
|
===============================================
|
|
| 245 | auto/auto |
|
|
===============================================
|
|
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|
Statistics for case statements in always block at line 258 in file
|
|
'../rtl/VX_decode.v'
|
|
===============================================
|
|
| Line | full/ parallel |
|
|
===============================================
|
|
| 259 | auto/auto |
|
|
| 264 | auto/auto |
|
|
===============================================
|
|
|
|
Statistics for case statements in always block at line 298 in file
|
|
'../rtl/VX_decode.v'
|
|
===============================================
|
|
| Line | full/ parallel |
|
|
===============================================
|
|
| 300 | auto/auto |
|
|
===============================================
|
|
|
|
Statistics for case statements in always block at line 313 in file
|
|
'../rtl/VX_decode.v'
|
|
===============================================
|
|
| Line | full/ parallel |
|
|
===============================================
|
|
| 315 | auto/auto |
|
|
===============================================
|
|
|
|
Statistics for case statements in always block at line 330 in file
|
|
'../rtl/VX_decode.v'
|
|
===============================================
|
|
| Line | full/ parallel |
|
|
===============================================
|
|
| 331 | auto/auto |
|
|
===============================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_d_e_reg' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
|
|
the parameters "|((N%clk%)(N%reset%)(N%in_branch_stall%)(N%in_freeze%)(N%VX_frE_to_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%))". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_mw_wb_inter'. (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_mem_req_inter'. (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_gpr_stage' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
|
|
the parameters "|((N%clk%)(N%reset%)(N%schedule_delay%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_csr_req%I%WORK/VX_csr_req_inter%%)(N%memory_delay%)(N%gpr_stage_delay%))". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_lsu' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
|
|
the parameters "|((N%clk%)(N%reset%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_mem_wb%I%WORK/VX_inst_mem_wb_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%out_delay%)(N%no_slot_mem%))". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_execute_unit' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
|
|
the parameters "|((N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_inst_exec_wb%I%WORK/VX_inst_exec_wb_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%))". (HDL-193)
|
|
Warning: ../rtl/VX_execute_unit.v:107: signed to unsigned assignment occurs. (VER-318)
|
|
Warning: ../rtl/VX_execute_unit.v:114: signed to unsigned assignment occurs. (VER-318)
|
|
|
|
Statistics for case statements in always block at line 74 in file
|
|
'../rtl/VX_execute_unit.v'
|
|
===============================================
|
|
| Line | full/ parallel |
|
|
===============================================
|
|
| 76 | auto/auto |
|
|
===============================================
|
|
Statistics for MUX_OPs
|
|
===========================================================================================================================================================================================================================
|
|
| block name/line | Inputs | Outputs | # sel inputs |
|
|
===========================================================================================================================================================================================================================
|
|
| VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__/71 | 4 | 32 | 2 |
|
|
===========================================================================================================================================================================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_gpgpu_inst' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
|
|
the parameters "|((N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%))". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_csr_wrapper' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
|
|
the parameters "|((N%VX_csr_req%I%WORK/VX_csr_req_inter%%)(N%VX_csr_wb%I%WORK/VX_csr_wb_inter%%))". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_writeback' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
|
|
the parameters "|((N%VX_mem_wb%I%WORK/VX_inst_mem_wb_inter%%)(N%VX_inst_exec_wb%I%WORK/VX_inst_exec_wb_inter%%)(N%VX_csr_wb%I%WORK/VX_csr_wb_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%no_slot_mem%))". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_shared_memory' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with
|
|
the parameters "NB=7,BITS_PER_BANK=3". (HDL-193)
|
|
|
|
Inferred memory devices in process
|
|
in routine VX_shared_memory_NB7_BITS_PER_BANK3 line 86 in file
|
|
'../rtl/shared_memory/VX_shared_memory.v'.
|
|
===========================================================================
|
|
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
|
===========================================================================
|
|
| temp_out_data_reg | Latch | 128 | Y | N | N | N | - | - | - |
|
|
| shm_write_reg | Latch | 1 | N | N | N | N | - | - | - |
|
|
| temp_out_valid_reg | Latch | 4 | Y | N | N | N | - | - | - |
|
|
===========================================================================
|
|
Statistics for MUX_OPs
|
|
=============================================================================
|
|
| block name/line | Inputs | Outputs | # sel inputs |
|
|
=============================================================================
|
|
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
|
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
|
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
|
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
|
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
|
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
|
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
|
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
|
=============================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_d_cache' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with
|
|
the parameters "CACHE_SIZE=4096,CACHE_WAYS=1,CACHE_BLOCK=128,CACHE_BANKS=8,NUM_REQ=4". (HDL-193)
|
|
Warning: ../rtl/cache/VX_d_cache.v:208: signed to unsigned assignment occurs. (VER-318)
|
|
|
|
Inferred memory devices in process
|
|
in routine VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4 line 219 in file
|
|
'../rtl/cache/VX_d_cache.v'.
|
|
===============================================================================
|
|
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
|
===============================================================================
|
|
| evict_addr_reg | Flip-flop | 29 | Y | N | Y | N | N | N | N |
|
|
| final_data_read_reg | Flip-flop | 128 | Y | N | Y | N | N | N | N |
|
|
| state_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N |
|
|
| stored_valid_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N |
|
|
| miss_addr_reg | Flip-flop | 29 | Y | N | Y | N | N | N | N |
|
|
===============================================================================
|
|
Statistics for MUX_OPs
|
|
====================================================================================================================
|
|
| block name/line | Inputs | Outputs | # sel inputs |
|
|
====================================================================================================================
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/240 | 8 | 2 | 3 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/240 | 4 | 29 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/241 | 8 | 29 | 3 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 |
|
|
| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 |
|
|
====================================================================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_warp_scheduler'. (HDL-193)
|
|
|
|
Inferred memory devices in process
|
|
in routine VX_warp_scheduler line 113 in file
|
|
'../rtl/VX_warp_scheduler.v'.
|
|
==================================================================================
|
|
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
|
==================================================================================
|
|
| thread_masks_reg | Flip-flop | 24 | Y | N | Y | N | N | N | N |
|
|
| thread_masks_reg | Flip-flop | 8 | Y | N | N | Y | N | N | N |
|
|
| warp_stalled_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N |
|
|
| barrier_stall_mask_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N |
|
|
| use_wsapwn_pc_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N |
|
|
| use_wsapwn_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N |
|
|
| warp_pcs_reg | Flip-flop | 227 | Y | N | Y | N | N | N | N |
|
|
| warp_pcs_reg | Flip-flop | 29 | Y | N | N | Y | N | N | N |
|
|
| warp_active_reg | Flip-flop | 7 | Y | N | Y | N | N | N | N |
|
|
| warp_active_reg | Flip-flop | 1 | N | N | N | Y | N | N | N |
|
|
| visible_active_reg | Flip-flop | 7 | Y | N | Y | N | N | N | N |
|
|
| visible_active_reg | Flip-flop | 1 | N | N | N | Y | N | N | N |
|
|
==================================================================================
|
|
Statistics for MUX_OPs
|
|
===========================================================
|
|
| block name/line | Inputs | Outputs | # sel inputs |
|
|
===========================================================
|
|
| VX_warp_scheduler/215 | 4 | 8 | 2 |
|
|
| VX_warp_scheduler/233 | 8 | 4 | 3 |
|
|
| VX_warp_scheduler/237 | 8 | 37 | 3 |
|
|
| VX_warp_scheduler/266 | 8 | 3 | 3 |
|
|
| VX_warp_scheduler/273 | 8 | 32 | 3 |
|
|
| VX_warp_scheduler/274 | 8 | 4 | 3 |
|
|
===========================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_generic_register' instantiated from design 'VX_f_d_reg_I_fe_inst_meta_fd_VX_inst_meta_inter__I_fd_inst_meta_de_VX_inst_meta_inter__' with
|
|
the parameters "N=71". (HDL-193)
|
|
|
|
Inferred memory devices in process
|
|
in routine VX_generic_register_N71 line 21 in file
|
|
'../rtl/VX_generic_register.v'.
|
|
===============================================================================
|
|
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
|
===============================================================================
|
|
| value_reg | Flip-flop | 71 | Y | N | Y | N | N | N | N |
|
|
===============================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_generic_register' instantiated from design 'VX_d_e_reg_I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
|
|
the parameters "N=240". (HDL-193)
|
|
|
|
Inferred memory devices in process
|
|
in routine VX_generic_register_N240 line 21 in file
|
|
'../rtl/VX_generic_register.v'.
|
|
===============================================================================
|
|
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
|
===============================================================================
|
|
| value_reg | Flip-flop | 240 | Y | N | Y | N | N | N | N |
|
|
===============================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_gpr_wrapper' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
|
the parameters "|((N%clk%)(N%reset%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%VX_gpr_read%I%WORK/VX_gpr_read_inter%%)(N%VX_gpr_jal%I%WORK/VX_gpr_jal_inter%%)(N%out_a_reg_data%)(N%out_b_reg_data%))". (HDL-193)
|
|
Statistics for MUX_OPs
|
|
==========================================================================================================================================================
|
|
| block name/line | Inputs | Outputs | # sel inputs |
|
|
==========================================================================================================================================================
|
|
| VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__/25 | 8 | 256 | 3 |
|
|
==========================================================================================================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_inst_multiplex' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
|
the parameters "|((N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_gpr_data%I%WORK/VX_gpr_data_inter%%)(N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_csr_req%I%WORK/VX_csr_req_inter%%))". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
|
the parameters "N=308". (HDL-193)
|
|
|
|
Inferred memory devices in process
|
|
in routine VX_generic_register_N308 line 21 in file
|
|
'../rtl/VX_generic_register.v'.
|
|
===============================================================================
|
|
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
|
===============================================================================
|
|
| value_reg | Flip-flop | 308 | Y | N | Y | N | N | N | N |
|
|
===============================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
|
the parameters "N=487". (HDL-193)
|
|
|
|
Inferred memory devices in process
|
|
in routine VX_generic_register_N487 line 21 in file
|
|
'../rtl/VX_generic_register.v'.
|
|
===============================================================================
|
|
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
|
===============================================================================
|
|
| value_reg | Flip-flop | 487 | Y | N | Y | N | N | N | N |
|
|
===============================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
|
the parameters "N=203". (HDL-193)
|
|
|
|
Inferred memory devices in process
|
|
in routine VX_generic_register_N203 line 21 in file
|
|
'../rtl/VX_generic_register.v'.
|
|
===============================================================================
|
|
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
|
===============================================================================
|
|
| value_reg | Flip-flop | 203 | Y | N | Y | N | N | N | N |
|
|
===============================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
|
the parameters "N=60". (HDL-193)
|
|
|
|
Inferred memory devices in process
|
|
in routine VX_generic_register_N60 line 21 in file
|
|
'../rtl/VX_generic_register.v'.
|
|
===============================================================================
|
|
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
|
===============================================================================
|
|
| value_reg | Flip-flop | 60 | Y | N | Y | N | N | N | N |
|
|
===============================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_lsu_addr_gen'. (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_alu'. (HDL-193)
|
|
Warning: ../rtl/VX_alu.v:40: signed to unsigned assignment occurs. (VER-318)
|
|
Warning: ../rtl/VX_alu.v:49: signed to unsigned assignment occurs. (VER-318)
|
|
Warning: ../rtl/VX_alu.v:50: signed to unsigned assignment occurs. (VER-318)
|
|
Warning: ../rtl/VX_alu.v:56: signed to unsigned assignment occurs. (VER-318)
|
|
Warning: ../rtl/VX_alu.v:61: signed to unsigned assignment occurs. (VER-318)
|
|
Warning: ../rtl/VX_alu.v:66: signed to unsigned conversion occurs. (VER-318)
|
|
Warning: ../rtl/VX_alu.v:68: signed to unsigned conversion occurs. (VER-318)
|
|
|
|
Statistics for case statements in always block at line 47 in file
|
|
'../rtl/VX_alu.v'
|
|
===============================================
|
|
| Line | full/ parallel |
|
|
===============================================
|
|
| 48 | auto/auto |
|
|
===============================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_generic_priority_encoder' instantiated from design 'VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__' with
|
|
the parameters "N=4". (HDL-193)
|
|
Warning: ../rtl/VX_generic_priority_encoder.v:17: signed to unsigned part selection occurs. (VER-318)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_countones' instantiated from design 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__' with
|
|
the parameters "N=4". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_priority_encoder_sm' instantiated from design 'VX_shared_memory_NB7_BITS_PER_BANK3' with
|
|
the parameters "NB=7,BITS_PER_BANK=3". (HDL-193)
|
|
|
|
Inferred memory devices in process
|
|
in routine VX_priority_encoder_sm_NB7_BITS_PER_BANK3 line 104 in file
|
|
'../rtl/shared_memory/VX_priority_encoder_sm.v'.
|
|
===============================================================================
|
|
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
|
===============================================================================
|
|
| left_requests_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N |
|
|
===============================================================================
|
|
Statistics for MUX_OPs
|
|
==================================================================================
|
|
| block name/line | Inputs | Outputs | # sel inputs |
|
|
==================================================================================
|
|
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
|
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
|
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
|
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
|
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
|
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
|
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
|
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
|
==================================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_shared_memory_block'. (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_cache_bank_valid' instantiated from design 'VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4' with
|
|
the parameters "NUMBER_BANKS=8". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_priority_encoder_w_mask' instantiated from design 'VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4' with
|
|
the parameters "N=4". (HDL-193)
|
|
Warning: ../rtl/VX_priority_encoder_w_mask.v:19: signed to unsigned part selection occurs. (VER-318)
|
|
Warning: ../rtl/VX_priority_encoder_w_mask.v:27: signed to unsigned assignment occurs. (VER-318)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_generic_priority_encoder' instantiated from design 'VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4' with
|
|
the parameters "N=8". (HDL-193)
|
|
Warning: ../rtl/VX_generic_priority_encoder.v:17: signed to unsigned part selection occurs. (VER-318)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_Cache_Bank' instantiated from design 'VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4' with
|
|
the parameters "CACHE_SIZE=4096,CACHE_WAYS=1,CACHE_BLOCK=128,CACHE_BANKS=8". (HDL-193)
|
|
Statistics for MUX_OPs
|
|
==============================================================================================================
|
|
| block name/line | Inputs | Outputs | # sel inputs |
|
|
==============================================================================================================
|
|
| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8/130 | 4 | 32 | 2 |
|
|
| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8/130 | 4 | 24 | 2 |
|
|
| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8/130 | 4 | 16 | 2 |
|
|
| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8/130 | 4 | 8 | 2 |
|
|
==============================================================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_countones' instantiated from design 'VX_warp_scheduler' with
|
|
the parameters "N=8". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_generic_stack' instantiated from design 'VX_warp_scheduler' with
|
|
the parameters "WIDTH=37,DEPTH=2". (HDL-193)
|
|
|
|
Inferred memory devices in process
|
|
in routine VX_generic_stack_WIDTH37_DEPTH2 line 21 in file
|
|
'../rtl/VX_generic_stack.v'.
|
|
===============================================================================
|
|
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
|
===============================================================================
|
|
| stack_reg | Flip-flop | 111 | Y | N | N | N | N | N | N |
|
|
| ptr_reg | Flip-flop | 2 | Y | N | N | N | N | N | N |
|
|
===============================================================================
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_priority_encoder'. (HDL-193)
|
|
Warning: ../rtl/VX_priority_encoder.v:15: signed to unsigned part selection occurs. (VER-318)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_gpr' instantiated from design 'VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__' with
|
|
the parameters "|((N%clk%)(N%reset%)(N%valid_write_request%)(N%VX_gpr_read%I%WORK/VX_gpr_read_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%out_a_reg_data%)(N%out_b_reg_data%))". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_bank_valids' instantiated from design 'VX_priority_encoder_sm_NB7_BITS_PER_BANK3' with
|
|
the parameters "NB=7,BITS_PER_BANK=3". (HDL-193)
|
|
Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318)
|
|
Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318)
|
|
Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318)
|
|
Presto compilation completed successfully.
|
|
Information: Building the design 'VX_cache_data' instantiated from design 'VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8' with
|
|
the parameters "CACHE_SIZE=4096,CACHE_WAYS=1,CACHE_BLOCK=128,CACHE_BANKS=8,NUM_WORDS_PER_BLOCK=4". (HDL-193)
|
|
Presto compilation completed successfully.
|
|
Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
|
|
Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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1
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link
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Linking design 'Vortex'
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Using the following designs and libraries:
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--------------------------------------------------------------------------
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* (44 designs) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/Vortex.db, etc
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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c (library) /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db
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USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db
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USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db
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USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db
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USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db
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dw_foundation.sldb (library) /tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/dw_foundation.sldb
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5)
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0
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set clk_freq 100
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100
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set clk_period [expr 1000.0 / $clk_freq / 1.0]
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10.0
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create_clock [get_ports clk] -period $clk_period
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1
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set_max_fanout 20 [get_ports clk]
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1
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set_ideal_network [get_ports clk]
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1
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set_max_fanout 20 [get_ports reset]
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1
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set_false_path -from [get_ports reset]
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1
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set_register_merging Vortex FALSE
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1
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set compile_seqmap_propagate_constants false
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false
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set compile_seqmap_propagate_high_effort false
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false
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compile_ultra -no_autoungroup
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Information: Performing power optimization. (PWR-850)
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Alib files are up-to-date.
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Information: Evaluating DesignWare library utilization. (UISN-27)
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============================================================================
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| DesignWare Building Block Library | Version | Available |
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============================================================================
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| Basic DW Building Blocks | O-2018.06-DWBB_201806.3 | * |
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| Licensed DW Building Blocks | O-2018.06-DWBB_201806.3 | * |
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============================================================================
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Information: Sequential output inversion is enabled. SVF file must be used for formal verification. (OPT-1208)
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Information: There are 9060 potential problems in your design. Please run 'check_design' for more information. (LINT-99)
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Information: Uniquified 4 instances of design 'VX_alu'. (OPT-1056)
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Information: Uniquified 9 instances of design 'VX_generic_priority_encoder_N4'. (OPT-1056)
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Information: Uniquified 9 instances of design 'VX_countones_N4'. (OPT-1056)
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Information: Uniquified 8 instances of design 'VX_shared_memory_block'. (OPT-1056)
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Information: Uniquified 8 instances of design 'VX_priority_encoder_w_mask_N4'. (OPT-1056)
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Information: Uniquified 8 instances of design 'VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8'. (OPT-1056)
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Information: Uniquified 2 instances of design 'VX_countones_N8'. (OPT-1056)
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Information: Uniquified 8 instances of design 'VX_generic_stack_WIDTH37_DEPTH2'. (OPT-1056)
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Information: Uniquified 8 instances of design 'VX_gpr_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__'. (OPT-1056)
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Information: Uniquified 8 instances of design 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (OPT-1056)
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Simplifying Design 'Vortex'
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_7'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_7'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_6'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_6'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_5'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_5'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_4'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_4'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_3'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_3'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_2'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_2'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_1'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_1'. (LINK-5)
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Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_0'. (LINK-3)
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Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_0'. (LINK-5)
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Loaded alib file './alib-52/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db.alib'
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Information: State dependent leakage is now switched from on to off.
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Beginning Pass 1 Mapping
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------------------------
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