Blaise Tine 04a1c0e9eb IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr

2021-05-01 13:44:08 -07:00

..

configs

project directories reorganization

2020-04-14 06:35:20 -04:00

dpi

fpu dpi update

2021-03-31 02:36:34 -07:00

models/memory

RTL code refactoring

2020-04-19 03:38:00 -04:00

rtl

IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr

2021-05-01 13:44:08 -07:00

scripts

code refactoring: DRAM => MEM renaming

2021-04-26 00:58:48 -07:00

simulate

minor update

2021-04-29 23:58:45 -07:00

syn

afu mem controller refactoring

2021-05-01 08:39:52 -07:00

unit_tests

code refactoring

2021-04-26 02:34:21 -07:00

.gitignore

adding dram writeenable support + scheduler bug fixes

2020-05-27 19:00:23 -04:00

Makefile

enabling 128-bit dram bus

2021-04-24 00:31:27 -04:00