d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
103 lines
3.0 KiB
Systemverilog
103 lines
3.0 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_pending_size #(
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parameter SIZE = 1,
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parameter INCRW = 1,
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parameter DECRW = 1,
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parameter SIZEW = `CLOG2(SIZE+1)
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) (
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input wire clk,
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input wire reset,
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input wire [INCRW-1:0] incr,
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input wire [DECRW-1:0] decr,
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output wire empty,
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output wire full,
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output wire [SIZEW-1:0] size
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);
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`STATIC_ASSERT(INCRW <= SIZEW, ("invalid parameter"))
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`STATIC_ASSERT(DECRW <= SIZEW, ("invalid parameter"))
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localparam ADDRW = `LOG2UP(SIZE);
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reg empty_r;
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reg full_r;
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if (INCRW != 1 || DECRW != 1) begin
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reg [SIZEW-1:0] size_r;
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wire [SIZEW-1:0] size_n;
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assign size_n = size_r + SIZEW'(incr) - SIZEW'(decr);
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always @(posedge clk) begin
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if (reset) begin
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size_r <= '0;
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empty_r <= 1;
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full_r <= 0;
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end else begin
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size_r <= size_n;
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empty_r <= (size_n == SIZEW'(0));
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full_r <= (size_n == SIZEW'(SIZE));
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end
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end
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assign size = size_r;
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end else begin
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reg [ADDRW-1:0] used_r;
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always @(posedge clk) begin
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if (reset) begin
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used_r <= '0;
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empty_r <= 1;
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full_r <= 0;
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end else begin
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`ASSERT(~(incr && ~decr) || ~full, ("runtime error: incrementing full counter"));
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`ASSERT(~(decr && ~incr) || ~empty, ("runtime error: decrementing empty counter"));
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if (incr) begin
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if (~decr) begin
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empty_r <= 0;
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if (used_r == ADDRW'(SIZE-1))
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full_r <= 1;
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end
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end else if (decr) begin
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full_r <= 0;
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if (used_r == ADDRW'(1))
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empty_r <= 1;
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end
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used_r <= $signed(used_r) + ADDRW'($signed(2'(incr) - 2'(decr)));
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end
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end
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if (SIZE > 1) begin
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if (SIZEW > ADDRW) begin
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assign size = {full_r, used_r};
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end else begin
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assign size = used_r;
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end
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end else begin
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assign size = full_r;
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end
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end
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assign empty = empty_r;
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assign full = full_r;
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endmodule
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`TRACING_ON
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