c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
491 lines
20 KiB
Systemverilog
491 lines
20 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_fpu_define.vh"
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`ifdef FPU_DPI
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module VX_fpu_dpi import VX_fpu_pkg::*; #(
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parameter NUM_LANES = 1,
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parameter TAGW = 1,
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parameter OUT_REG = 0
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [NUM_LANES-1:0] lane_mask,
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input wire [TAGW-1:0] tag_in,
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input wire [`INST_FPU_BITS-1:0] op_type,
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input wire [`INST_FMT_BITS-1:0] fmt,
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input wire [`INST_FRM_BITS-1:0] frm,
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input wire [NUM_LANES-1:0][`XLEN-1:0] dataa,
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input wire [NUM_LANES-1:0][`XLEN-1:0] datab,
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input wire [NUM_LANES-1:0][`XLEN-1:0] datac,
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output wire [NUM_LANES-1:0][`XLEN-1:0] result,
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output wire has_fflags,
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output wire [`FP_FLAGS_BITS-1:0] fflags,
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output wire [TAGW-1:0] tag_out,
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input wire ready_out,
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output wire valid_out
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);
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localparam FPU_FMA = 0;
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localparam FPU_DIVSQRT = 1;
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localparam FPU_CVT = 2;
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localparam FPU_NCP = 3;
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localparam NUM_FPC = 4;
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localparam FPC_BITS = `LOG2UP(NUM_FPC);
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localparam RSP_DATAW = (NUM_LANES * `XLEN) + 1 + $bits(fflags_t) + TAGW;
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wire [NUM_FPC-1:0] per_core_ready_in;
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wire [NUM_FPC-1:0][NUM_LANES-1:0][`XLEN-1:0] per_core_result;
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wire [NUM_FPC-1:0][TAGW-1:0] per_core_tag_out;
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reg [NUM_FPC-1:0] per_core_ready_out;
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wire [NUM_FPC-1:0] per_core_valid_out;
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wire [NUM_FPC-1:0] per_core_has_fflags;
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fflags_t [NUM_FPC-1:0] per_core_fflags;
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wire div_ready_in, sqrt_ready_in;
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wire [NUM_LANES-1:0][`XLEN-1:0] div_result, sqrt_result;
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wire [TAGW-1:0] div_tag_out, sqrt_tag_out;
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wire div_ready_out, sqrt_ready_out;
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wire div_valid_out, sqrt_valid_out;
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wire div_has_fflags, sqrt_has_fflags;
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fflags_t div_fflags, sqrt_fflags;
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reg [FPC_BITS-1:0] core_select;
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reg is_fadd, is_fsub, is_fmul, is_fmadd, is_fmsub, is_fnmadd, is_fnmsub;
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reg is_div, is_fcmp, is_itof, is_utof, is_ftoi, is_ftou, is_f2f;
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reg dst_fmt, int_fmt;
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reg [NUM_LANES-1:0][63:0] operands [3];
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always @(*) begin
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for (integer i = 0; i < NUM_LANES; ++i) begin
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operands[0][i] = 64'(dataa[i]);
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operands[1][i] = 64'(datab[i]);
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operands[2][i] = 64'(datac[i]);
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end
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end
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`UNUSED_VAR (fmt)
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always @(*) begin
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is_fadd = 0;
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is_fsub = 0;
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is_fmul = 0;
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is_fmadd = 0;
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is_fmsub = 0;
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is_fnmadd = 0;
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is_fnmsub = 0;
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is_div = 0;
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is_fcmp = 0;
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is_itof = 0;
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is_utof = 0;
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is_ftoi = 0;
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is_ftou = 0;
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is_f2f = 0;
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dst_fmt = 0;
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int_fmt = 0;
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`ifdef FLEN_64
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dst_fmt = fmt[0];
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`endif
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`ifdef XLEN_64
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int_fmt = fmt[1];
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`endif
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case (op_type)
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`INST_FPU_ADD: begin core_select = FPU_FMA; is_fadd = 1; end
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`INST_FPU_SUB: begin core_select = FPU_FMA; is_fsub = 1; end
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`INST_FPU_MUL: begin core_select = FPU_FMA; is_fmul = 1; end
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`INST_FPU_MADD: begin core_select = FPU_FMA; is_fmadd = 1; end
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`INST_FPU_MSUB: begin core_select = FPU_FMA; is_fmsub = 1; end
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`INST_FPU_NMADD: begin core_select = FPU_FMA; is_fnmadd = 1; end
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`INST_FPU_NMSUB: begin core_select = FPU_FMA; is_fnmsub = 1; end
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`INST_FPU_DIV: begin core_select = FPU_DIVSQRT; is_div = 1; end
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`INST_FPU_SQRT: begin core_select = FPU_DIVSQRT; end
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`INST_FPU_CMP: begin core_select = FPU_NCP; is_fcmp = 1; end
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`INST_FPU_F2I: begin core_select = FPU_CVT; is_ftoi = 1; end
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`INST_FPU_F2U: begin core_select = FPU_CVT; is_ftou = 1; end
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`INST_FPU_I2F: begin core_select = FPU_CVT; is_itof = 1; end
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`INST_FPU_U2F: begin core_select = FPU_CVT; is_utof = 1; end
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`INST_FPU_F2F: begin core_select = FPU_CVT; is_f2f = 1; end
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default: begin core_select = FPU_NCP; end
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endcase
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end
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generate
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begin : fma
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reg [NUM_LANES-1:0][`XLEN-1:0] result_fma;
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wire [NUM_LANES-1:0][63:0] result_fadd;
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wire [NUM_LANES-1:0][63:0] result_fsub;
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wire [NUM_LANES-1:0][63:0] result_fmul;
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wire [NUM_LANES-1:0][63:0] result_fmadd;
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wire [NUM_LANES-1:0][63:0] result_fmsub;
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wire [NUM_LANES-1:0][63:0] result_fnmadd;
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wire [NUM_LANES-1:0][63:0] result_fnmsub;
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fflags_t [NUM_LANES-1:0] fflags_fma;
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fflags_t [NUM_LANES-1:0] fflags_fadd;
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fflags_t [NUM_LANES-1:0] fflags_fsub;
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fflags_t [NUM_LANES-1:0] fflags_fmul;
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fflags_t [NUM_LANES-1:0] fflags_fmadd;
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fflags_t [NUM_LANES-1:0] fflags_fmsub;
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fflags_t [NUM_LANES-1:0] fflags_fnmadd;
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fflags_t [NUM_LANES-1:0] fflags_fnmsub;
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wire fma_valid = (valid_in && core_select == FPU_FMA);
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wire fma_ready = per_core_ready_out[FPU_FMA] || ~per_core_valid_out[FPU_FMA];
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wire fma_fire = fma_valid && fma_ready;
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always @(*) begin
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for (integer i = 0; i < NUM_LANES; ++i) begin
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dpi_fadd (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fadd[i], fflags_fadd[i]);
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dpi_fsub (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fsub[i], fflags_fsub[i]);
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dpi_fmul (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fmul[i], fflags_fmul[i]);
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dpi_fmadd (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fmadd[i], fflags_fmadd[i]);
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dpi_fmsub (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fmsub[i], fflags_fmsub[i]);
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dpi_fnmadd (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fnmadd[i], fflags_fnmadd[i]);
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dpi_fnmsub (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fnmsub[i], fflags_fnmsub[i]);
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result_fma[i] = is_fadd ? result_fadd[i][`XLEN-1:0] :
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is_fsub ? result_fsub[i][`XLEN-1:0] :
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is_fmul ? result_fmul[i][`XLEN-1:0] :
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is_fmadd ? result_fmadd[i][`XLEN-1:0] :
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is_fmsub ? result_fmsub[i][`XLEN-1:0] :
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is_fnmadd ? result_fnmadd[i][`XLEN-1:0] :
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is_fnmsub ? result_fnmsub[i][`XLEN-1:0] :
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'0;
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fflags_fma[i] = is_fadd ? fflags_fadd[i] :
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is_fsub ? fflags_fsub[i] :
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is_fmul ? fflags_fmul[i] :
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is_fmadd ? fflags_fmadd[i] :
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is_fmsub ? fflags_fmsub[i] :
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is_fnmadd ? fflags_fnmadd[i] :
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is_fnmsub ? fflags_fnmsub[i] :
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'0;
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end
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end
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fflags_t fflags_merged;
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`FPU_MERGE_FFLAGS(fflags_merged, fflags_fma, lane_mask, NUM_LANES);
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VX_shift_register #(
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.DATAW (1 + TAGW + NUM_LANES * `XLEN + $bits(fflags_t)),
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.DEPTH (`LATENCY_FMA),
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.RESETW (1)
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) shift_reg (
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.clk (clk),
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.reset (reset),
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.enable (fma_ready),
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.data_in ({fma_valid, tag_in, result_fma, fflags_merged}),
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.data_out ({per_core_valid_out[FPU_FMA], per_core_tag_out[FPU_FMA], per_core_result[FPU_FMA], per_core_fflags[FPU_FMA]})
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);
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assign per_core_has_fflags[FPU_FMA] = 1;
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assign per_core_ready_in[FPU_FMA] = fma_ready;
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end
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endgenerate
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generate
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begin : fdiv
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reg [NUM_LANES-1:0][`XLEN-1:0] result_fdiv_r;
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wire [NUM_LANES-1:0][63:0] result_fdiv;
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fflags_t [NUM_LANES-1:0] fflags_fdiv;
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wire fdiv_valid = (valid_in && core_select == FPU_DIVSQRT) && is_div;
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wire fdiv_ready = div_ready_out || ~div_valid_out;
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wire fdiv_fire = fdiv_valid && fdiv_ready;
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always @(*) begin
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for (integer i = 0; i < NUM_LANES; ++i) begin
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dpi_fdiv (fdiv_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fdiv[i], fflags_fdiv[i]);
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result_fdiv_r[i] = result_fdiv[i][`XLEN-1:0];
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end
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end
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fflags_t fflags_merged;
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`FPU_MERGE_FFLAGS(fflags_merged, fflags_fdiv, lane_mask, NUM_LANES);
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VX_shift_register #(
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.DATAW (1 + TAGW + NUM_LANES * `XLEN + $bits(fflags_t)),
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.DEPTH (`LATENCY_FDIV),
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.RESETW (1)
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) shift_reg (
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.clk (clk),
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.reset (reset),
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.enable (fdiv_ready),
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.data_in ({fdiv_valid, tag_in, result_fdiv_r, fflags_merged}),
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.data_out ({div_valid_out, div_tag_out, div_result, div_fflags})
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);
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assign div_has_fflags = 1;
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assign div_ready_in = fdiv_ready;
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end
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endgenerate
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generate
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begin : fsqrt
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reg [NUM_LANES-1:0][`XLEN-1:0] result_fsqrt_r;
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wire [NUM_LANES-1:0][63:0] result_fsqrt;
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fflags_t [NUM_LANES-1:0] fflags_fsqrt;
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wire fsqrt_valid = (valid_in && core_select == FPU_DIVSQRT) && ~is_div;
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wire fsqrt_ready = sqrt_ready_out || ~sqrt_valid_out;
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wire fsqrt_fire = fsqrt_valid && fsqrt_ready;
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always @(*) begin
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for (integer i = 0; i < NUM_LANES; ++i) begin
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dpi_fsqrt (fsqrt_fire, int'(dst_fmt), operands[0][i], frm, result_fsqrt[i], fflags_fsqrt[i]);
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result_fsqrt_r[i] = result_fsqrt[i][`XLEN-1:0];
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end
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end
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fflags_t fflags_merged;
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`FPU_MERGE_FFLAGS(fflags_merged, fflags_fsqrt, lane_mask, NUM_LANES);
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VX_shift_register #(
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.DATAW (1 + TAGW + NUM_LANES * `XLEN + $bits(fflags_t)),
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.DEPTH (`LATENCY_FSQRT),
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.RESETW (1)
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) shift_reg (
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.clk (clk),
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.reset (reset),
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.enable (fsqrt_ready),
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.data_in ({fsqrt_valid, tag_in, result_fsqrt_r, fflags_merged}),
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.data_out ({sqrt_valid_out, sqrt_tag_out, sqrt_result, sqrt_fflags})
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);
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assign sqrt_has_fflags = 1;
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assign sqrt_ready_in = fsqrt_ready;
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end
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endgenerate
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generate
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begin : fcvt
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reg [NUM_LANES-1:0][`XLEN-1:0] result_fcvt;
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wire [NUM_LANES-1:0][63:0] result_itof;
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wire [NUM_LANES-1:0][63:0] result_utof;
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wire [NUM_LANES-1:0][63:0] result_ftoi;
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wire [NUM_LANES-1:0][63:0] result_ftou;
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wire [NUM_LANES-1:0][63:0] result_f2f;
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fflags_t [NUM_LANES-1:0] fflags_fcvt;
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fflags_t [NUM_LANES-1:0] fflags_itof;
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fflags_t [NUM_LANES-1:0] fflags_utof;
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fflags_t [NUM_LANES-1:0] fflags_ftoi;
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fflags_t [NUM_LANES-1:0] fflags_ftou;
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wire fcvt_valid = (valid_in && core_select == FPU_CVT);
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wire fcvt_ready = per_core_ready_out[FPU_CVT] || ~per_core_valid_out[FPU_CVT];
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wire fcvt_fire = fcvt_valid && fcvt_ready;
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always @(*) begin
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for (integer i = 0; i < NUM_LANES; ++i) begin
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dpi_itof (fcvt_fire, int'(dst_fmt), int'(int_fmt), operands[0][i], frm, result_itof[i], fflags_itof[i]);
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dpi_utof (fcvt_fire, int'(dst_fmt), int'(int_fmt), operands[0][i], frm, result_utof[i], fflags_utof[i]);
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dpi_ftoi (fcvt_fire, int'(int_fmt), int'(dst_fmt), operands[0][i], frm, result_ftoi[i], fflags_ftoi[i]);
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dpi_ftou (fcvt_fire, int'(int_fmt), int'(dst_fmt), operands[0][i], frm, result_ftou[i], fflags_ftou[i]);
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dpi_f2f (fcvt_fire, int'(dst_fmt), operands[0][i], result_f2f[i]);
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result_fcvt[i] = is_itof ? result_itof[i][`XLEN-1:0] :
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is_utof ? result_utof[i][`XLEN-1:0] :
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is_ftoi ? result_ftoi[i][`XLEN-1:0] :
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is_ftou ? result_ftou[i][`XLEN-1:0] :
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is_f2f ? result_f2f[i][`XLEN-1:0] :
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'0;
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fflags_fcvt[i] = is_itof ? fflags_itof[i] :
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is_utof ? fflags_utof[i] :
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is_ftoi ? fflags_ftoi[i] :
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is_ftou ? fflags_ftou[i] :
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'0;
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end
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end
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fflags_t fflags_merged;
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`FPU_MERGE_FFLAGS(fflags_merged, fflags_fcvt, lane_mask, NUM_LANES);
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VX_shift_register #(
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.DATAW (1 + TAGW + NUM_LANES * `XLEN + $bits(fflags_t)),
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.DEPTH (`LATENCY_FCVT),
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.RESETW (1)
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) shift_reg (
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.clk (clk),
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.reset (reset),
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.enable (fcvt_ready),
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.data_in ({fcvt_valid, tag_in, result_fcvt, fflags_merged}),
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.data_out ({per_core_valid_out[FPU_CVT], per_core_tag_out[FPU_CVT], per_core_result[FPU_CVT], per_core_fflags[FPU_CVT]})
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);
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assign per_core_has_fflags[FPU_CVT] = 1;
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assign per_core_ready_in[FPU_CVT] = fcvt_ready;
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end
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endgenerate
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generate
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begin : fncp
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reg [NUM_LANES-1:0][`XLEN-1:0] result_fncp;
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wire [NUM_LANES-1:0][63:0] result_fclss;
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wire [NUM_LANES-1:0][63:0] result_flt;
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wire [NUM_LANES-1:0][63:0] result_fle;
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wire [NUM_LANES-1:0][63:0] result_feq;
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wire [NUM_LANES-1:0][63:0] result_fmin;
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wire [NUM_LANES-1:0][63:0] result_fmax;
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wire [NUM_LANES-1:0][63:0] result_fsgnj;
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wire [NUM_LANES-1:0][63:0] result_fsgnjn;
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wire [NUM_LANES-1:0][63:0] result_fsgnjx;
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reg [NUM_LANES-1:0][63:0] result_fmvx;
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reg [NUM_LANES-1:0][63:0] result_fmvf;
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fflags_t [NUM_LANES-1:0] fflags_fncp;
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fflags_t [NUM_LANES-1:0] fflags_flt;
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fflags_t [NUM_LANES-1:0] fflags_fle;
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fflags_t [NUM_LANES-1:0] fflags_feq;
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fflags_t [NUM_LANES-1:0] fflags_fmin;
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fflags_t [NUM_LANES-1:0] fflags_fmax;
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wire fncp_valid = (valid_in && core_select == FPU_NCP);
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wire fncp_ready = per_core_ready_out[FPU_NCP] || ~per_core_valid_out[FPU_NCP];
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wire fncp_fire = fncp_valid && fncp_ready;
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always @(*) begin
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for (integer i = 0; i < NUM_LANES; ++i) begin
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dpi_fclss (fncp_fire, int'(dst_fmt), operands[0][i], result_fclss[i]);
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dpi_fle (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fle[i], fflags_fle[i]);
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dpi_flt (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_flt[i], fflags_flt[i]);
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dpi_feq (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_feq[i], fflags_feq[i]);
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dpi_fmin (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fmin[i], fflags_fmin[i]);
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dpi_fmax (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fmax[i], fflags_fmax[i]);
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dpi_fsgnj (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fsgnj[i]);
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dpi_fsgnjn (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fsgnjn[i]);
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dpi_fsgnjx (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fsgnjx[i]);
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result_fmvx[i] = dst_fmt ? operands[0][i] : 64'($signed(operands[0][i][31:0])); // sign-extension
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result_fmvf[i] = dst_fmt ? operands[0][i] : (operands[0][i] | 64'hffffffff00000000); // nan-boxing
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end
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end
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always @(*) begin
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result_fncp = 'x;
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fflags_fncp = 'x;
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for (integer i = 0; i < NUM_LANES; ++i) begin
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case (frm)
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0: begin result_fncp[i] = is_fcmp ? result_fle[i][`XLEN-1:0] : result_fsgnj[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fle[i]; end
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1: begin result_fncp[i] = is_fcmp ? result_flt[i][`XLEN-1:0] : result_fsgnjn[i][`XLEN-1:0]; fflags_fncp[i] = fflags_flt[i]; end
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2: begin result_fncp[i] = is_fcmp ? result_feq[i][`XLEN-1:0] : result_fsgnjx[i][`XLEN-1:0]; fflags_fncp[i] = fflags_feq[i]; end
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3: begin result_fncp[i] = result_fclss[i][`XLEN-1:0]; end
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4: begin result_fncp[i] = result_fmvx[i][`XLEN-1:0]; end
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5: begin result_fncp[i] = result_fmvf[i][`XLEN-1:0]; end
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6: begin result_fncp[i] = result_fmin[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fmin[i]; end
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7: begin result_fncp[i] = result_fmax[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fmax[i]; end
|
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endcase
|
|
end
|
|
end
|
|
|
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fflags_t fflags_merged;
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`FPU_MERGE_FFLAGS(fflags_merged, fflags_fncp, lane_mask, NUM_LANES);
|
|
|
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wire has_fflags_fncp = (frm >= 6) || is_fcmp;
|
|
|
|
VX_shift_register #(
|
|
.DATAW (1 + TAGW + 1 + NUM_LANES * `XLEN + $bits(fflags_t)),
|
|
.DEPTH (`LATENCY_FNCP),
|
|
.RESETW (1)
|
|
) shift_reg (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.enable (fncp_ready),
|
|
.data_in ({fncp_valid, tag_in, has_fflags_fncp, result_fncp, fflags_merged}),
|
|
.data_out ({per_core_valid_out[FPU_NCP], per_core_tag_out[FPU_NCP], per_core_has_fflags[FPU_NCP], per_core_result[FPU_NCP], per_core_fflags[FPU_NCP]})
|
|
);
|
|
|
|
assign per_core_ready_in[FPU_NCP] = fncp_ready;
|
|
|
|
end
|
|
endgenerate
|
|
|
|
///////////////////////////////////////////////////////////////////////////
|
|
|
|
assign per_core_ready_in[FPU_DIVSQRT] = is_div ? div_ready_in : sqrt_ready_in;
|
|
|
|
VX_stream_arb #(
|
|
.NUM_INPUTS (2),
|
|
.DATAW (RSP_DATAW),
|
|
.ARBITER ("R"),
|
|
.OUT_REG (0)
|
|
) div_sqrt_arb (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.valid_in ({sqrt_valid_out, div_valid_out}),
|
|
.ready_in ({sqrt_ready_out, div_ready_out}),
|
|
.data_in ({{sqrt_result, sqrt_has_fflags, sqrt_fflags, sqrt_tag_out},
|
|
{div_result, div_has_fflags, div_fflags, div_tag_out}}),
|
|
.data_out ({per_core_result[FPU_DIVSQRT], per_core_has_fflags[FPU_DIVSQRT], per_core_fflags[FPU_DIVSQRT], per_core_tag_out[FPU_DIVSQRT]}),
|
|
.valid_out (per_core_valid_out[FPU_DIVSQRT]),
|
|
.ready_out (per_core_ready_out[FPU_DIVSQRT]),
|
|
`UNUSED_PIN (sel_out)
|
|
);
|
|
|
|
///////////////////////////////////////////////////////////////////////////
|
|
|
|
wire [NUM_FPC-1:0][RSP_DATAW-1:0] per_core_data_out;
|
|
|
|
for (genvar i = 0; i < NUM_FPC; ++i) begin
|
|
assign per_core_data_out[i] = {per_core_result[i], per_core_has_fflags[i], per_core_fflags[i], per_core_tag_out[i]};
|
|
end
|
|
|
|
VX_stream_arb #(
|
|
.NUM_INPUTS (NUM_FPC),
|
|
.DATAW (RSP_DATAW),
|
|
.ARBITER ("R"),
|
|
.OUT_REG (OUT_REG)
|
|
) rsp_arb (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.valid_in (per_core_valid_out),
|
|
.ready_in (per_core_ready_out),
|
|
.data_in (per_core_data_out),
|
|
.data_out ({result, has_fflags, fflags, tag_out}),
|
|
.valid_out (valid_out),
|
|
.ready_out (ready_out),
|
|
`UNUSED_PIN (sel_out)
|
|
);
|
|
|
|
assign ready_in = per_core_ready_in[core_select];
|
|
|
|
endmodule
|
|
`endif
|