// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Tracing implementation internals
#include "verilated_vcd_c.h"
#include "Vcache_simX__Syms.h"


//======================

void Vcache_simX::traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code) {
    // Callback from vcd->dump()
    Vcache_simX* t=(Vcache_simX*)userthis;
    Vcache_simX__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table
    if (vlSymsp->getClearActivity()) {
	t->traceChgThis (vlSymsp, vcdp, code);
    }
}

//======================


void Vcache_simX::traceChgThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    int c=code;
    if (0 && vcdp && c) {}  // Prevent unused
    // Body
    {
	if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity 
			       | (vlTOPp->__Vm_traceActivity 
				  >> 1U))))) {
	    vlTOPp->traceChgThis__2(vlSymsp, vcdp, code);
	}
	if (VL_UNLIKELY((1U & ((vlTOPp->__Vm_traceActivity 
				| (vlTOPp->__Vm_traceActivity 
				   >> 1U)) | (vlTOPp->__Vm_traceActivity 
					      >> 2U))))) {
	    vlTOPp->traceChgThis__3(vlSymsp, vcdp, code);
	}
	if (VL_UNLIKELY((1U & (((vlTOPp->__Vm_traceActivity 
				 | (vlTOPp->__Vm_traceActivity 
				    >> 1U)) | (vlTOPp->__Vm_traceActivity 
					       >> 2U)) 
			       | (vlTOPp->__Vm_traceActivity 
				  >> 3U))))) {
	    vlTOPp->traceChgThis__4(vlSymsp, vcdp, code);
	}
	if (VL_UNLIKELY((1U & ((vlTOPp->__Vm_traceActivity 
				| (vlTOPp->__Vm_traceActivity 
				   >> 1U)) | (vlTOPp->__Vm_traceActivity 
					      >> 3U))))) {
	    vlTOPp->traceChgThis__5(vlSymsp, vcdp, code);
	}
	if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity 
			       | (vlTOPp->__Vm_traceActivity 
				  >> 2U))))) {
	    vlTOPp->traceChgThis__6(vlSymsp, vcdp, code);
	}
	if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity 
			       | (vlTOPp->__Vm_traceActivity 
				  >> 3U))))) {
	    vlTOPp->traceChgThis__7(vlSymsp, vcdp, code);
	}
	if (VL_UNLIKELY((4U & vlTOPp->__Vm_traceActivity))) {
	    vlTOPp->traceChgThis__8(vlSymsp, vcdp, code);
	}
	vlTOPp->traceChgThis__9(vlSymsp, vcdp, code);
    }
    // Final
    vlTOPp->__Vm_traceActivity = 0U;
}

void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    int c=code;
    if (0 && vcdp && c) {}  // Prevent unused
    // Variables
    VL_SIGW(__Vtemp379,127,0,4);
    VL_SIGW(__Vtemp380,127,0,4);
    VL_SIGW(__Vtemp381,127,0,4);
    VL_SIGW(__Vtemp382,127,0,4);
    VL_SIGW(__Vtemp383,127,0,4);
    VL_SIGW(__Vtemp384,127,0,4);
    VL_SIGW(__Vtemp385,127,0,4);
    VL_SIGW(__Vtemp386,127,0,4);
    VL_SIGW(__Vtemp387,127,0,4);
    VL_SIGW(__Vtemp388,127,0,4);
    VL_SIGW(__Vtemp389,127,0,4);
    VL_SIGW(__Vtemp390,127,0,4);
    VL_SIGW(__Vtemp391,127,0,4);
    VL_SIGW(__Vtemp392,127,0,4);
    VL_SIGW(__Vtemp393,127,0,4);
    VL_SIGW(__Vtemp394,127,0,4);
    VL_SIGW(__Vtemp395,127,0,4);
    VL_SIGW(__Vtemp396,127,0,4);
    VL_SIGW(__Vtemp397,127,0,4);
    VL_SIGW(__Vtemp398,127,0,4);
    VL_SIGW(__Vtemp399,127,0,4);
    VL_SIGW(__Vtemp400,127,0,4);
    VL_SIGW(__Vtemp401,127,0,4);
    VL_SIGW(__Vtemp402,127,0,4);
    VL_SIGW(__Vtemp403,127,0,4);
    VL_SIGW(__Vtemp404,127,0,4);
    VL_SIGW(__Vtemp405,127,0,4);
    VL_SIGW(__Vtemp406,127,0,4);
    VL_SIGW(__Vtemp407,127,0,4);
    VL_SIGW(__Vtemp408,127,0,4);
    VL_SIGW(__Vtemp409,127,0,4);
    VL_SIGW(__Vtemp410,127,0,4);
    VL_SIGW(__Vtemp411,127,0,4);
    VL_SIGW(__Vtemp412,127,0,4);
    VL_SIGW(__Vtemp413,127,0,4);
    VL_SIGW(__Vtemp414,127,0,4);
    VL_SIGW(__Vtemp415,127,0,4);
    VL_SIGW(__Vtemp416,127,0,4);
    VL_SIGW(__Vtemp417,127,0,4);
    VL_SIGW(__Vtemp418,127,0,4);
    VL_SIGW(__Vtemp419,127,0,4);
    VL_SIGW(__Vtemp420,127,0,4);
    VL_SIGW(__Vtemp421,127,0,4);
    VL_SIGW(__Vtemp426,127,0,4);
    // Body
    {
	vcdp->chgBit  (c+1,((0xffU == (0xffU & ((vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[1U] 
						 << 8U) 
						| (vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[0U] 
						   >> 0x18U))))));
	vcdp->chgBus  (c+2,(vlSymsp->TOP__v__dmem_controller.__PVT__sm_driver_in_valid),4);
	vcdp->chgBus  (c+3,(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_valid),4);
	vcdp->chgBus  (c+11,(vlSymsp->TOP__v__dmem_controller.__PVT__sm_driver_in_mem_read),3);
	vcdp->chgBus  (c+12,(vlSymsp->TOP__v__dmem_controller.__PVT__sm_driver_in_mem_write),3);
	__Vtemp379[0U] = (((~ (IData)((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
			   & (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__orig_in_valid)))
			   ? vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__temp_out_data[0U]
			   : 0U);
	__Vtemp379[1U] = (((~ (IData)((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
			   & (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__orig_in_valid)))
			   ? vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__temp_out_data[1U]
			   : 0U);
	__Vtemp379[2U] = (((~ (IData)((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
			   & (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__orig_in_valid)))
			   ? vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__temp_out_data[2U]
			   : 0U);
	__Vtemp379[3U] = (((~ (IData)((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
			   & (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__orig_in_valid)))
			   ? vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__temp_out_data[3U]
			   : 0U);
	vcdp->chgArray(c+17,(__Vtemp379),128);
	vcdp->chgBus  (c+21,((0xfU & (((~ (IData)((0U 
						   != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
				       & (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__orig_in_valid)))
				       ? (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__temp_out_valid)
				       : 0U))),4);
	vcdp->chgArray(c+24,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address),128);
	vcdp->chgArray(c+28,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data),128);
	vcdp->chgBus  (c+33,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__temp_out_valid),4);
	vcdp->chgArray(c+34,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__temp_out_data),128);
	vcdp->chgBus  (c+38,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_addr),28);
	vcdp->chgArray(c+39,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata),512);
	vcdp->chgArray(c+55,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_rdata),512);
	vcdp->chgBus  (c+71,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_we),8);
	vcdp->chgBit  (c+72,(((~ (IData)((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
			      & (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__orig_in_valid)))));
	vcdp->chgBus  (c+73,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num),12);
	vcdp->chgBus  (c+74,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__orig_in_valid),4);
	vcdp->chgBit  (c+75,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write));
	vcdp->chgBit  (c+76,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write));
	vcdp->chgBit  (c+77,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write));
	vcdp->chgBit  (c+78,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write));
	vcdp->chgBit  (c+22,((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))));
	vcdp->chgBus  (c+79,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced),4);
	vcdp->chgBus  (c+80,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid),4);
	vcdp->chgBus  (c+81,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids),16);
	vcdp->chgBus  (c+82,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid),4);
	vcdp->chgBus  (c+83,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num),8);
	vcdp->chgBus  (c+32,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid),4);
	vcdp->chgBus  (c+84,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual),4);
	vcdp->chgBus  (c+85,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids),3);
	vcdp->chgBus  (c+86,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids),3);
	vcdp->chgBus  (c+87,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids),3);
	vcdp->chgBus  (c+88,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids),3);
	vcdp->chgBus  (c+89,((0xfU & (IData)(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))),4);
	vcdp->chgBus  (c+90,((0xfU & ((IData)(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) 
				      >> 4U))),4);
	vcdp->chgBus  (c+91,((0xfU & ((IData)(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) 
				      >> 8U))),4);
	vcdp->chgBus  (c+92,((0xfU & ((IData)(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) 
				      >> 0xcU))),4);
	vcdp->chgBus  (c+93,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index),2);
	vcdp->chgBit  (c+94,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found));
	vcdp->chgBus  (c+95,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i),32);
	vcdp->chgBus  (c+96,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index),2);
	vcdp->chgBit  (c+97,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found));
	vcdp->chgBus  (c+98,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i),32);
	vcdp->chgBus  (c+99,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index),2);
	vcdp->chgBit  (c+100,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found));
	vcdp->chgBus  (c+101,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i),32);
	vcdp->chgBus  (c+102,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index),2);
	vcdp->chgBit  (c+103,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found));
	vcdp->chgBus  (c+104,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i),32);
	vcdp->chgBus  (c+105,((0x7fU & vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_addr)),7);
	__Vtemp380[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[0U];
	__Vtemp380[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[1U];
	__Vtemp380[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[2U];
	__Vtemp380[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[3U];
	vcdp->chgArray(c+106,(__Vtemp380),128);
	vcdp->chgBus  (c+110,((3U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_we))),2);
	vcdp->chgArray(c+111,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_shared_memory_block__data_out),128);
	vcdp->chgBus  (c+115,((0x7fU & (vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_addr 
					>> 7U))),7);
	__Vtemp381[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[4U];
	__Vtemp381[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[5U];
	__Vtemp381[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[6U];
	__Vtemp381[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[7U];
	vcdp->chgArray(c+116,(__Vtemp381),128);
	vcdp->chgBus  (c+120,((3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_we) 
				     >> 2U))),2);
	vcdp->chgArray(c+121,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_shared_memory_block__data_out),128);
	vcdp->chgBus  (c+125,((0x7fU & (vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_addr 
					>> 0xeU))),7);
	__Vtemp382[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[8U];
	__Vtemp382[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[9U];
	__Vtemp382[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[0xaU];
	__Vtemp382[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[0xbU];
	vcdp->chgArray(c+126,(__Vtemp382),128);
	vcdp->chgBus  (c+130,((3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_we) 
				     >> 4U))),2);
	vcdp->chgArray(c+131,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_shared_memory_block__data_out),128);
	vcdp->chgBus  (c+135,((0x7fU & (vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_addr 
					>> 0x15U))),7);
	__Vtemp383[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[0xcU];
	__Vtemp383[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[0xdU];
	__Vtemp383[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[0xeU];
	__Vtemp383[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_wdata[0xfU];
	vcdp->chgArray(c+136,(__Vtemp383),128);
	vcdp->chgBus  (c+140,((3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_we) 
				     >> 6U))),2);
	vcdp->chgArray(c+141,(vlSymsp->TOP__v__dmem_controller.shared_memory__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_shared_memory_block__data_out),128);
	vcdp->chgBus  (c+145,((0xffffffc0U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__eviction_addr_per_bank[0U])),32);
	vcdp->chgArray(c+146,(vlSymsp->TOP__v__dmem_controller.__Vcellout__dcache__o_m_writedata),512);
	vcdp->chgArray(c+162,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_final_data_read),128);
	vcdp->chgArray(c+13,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_final_data_read_Qual),128);
	vcdp->chgBus  (c+166,(vlSymsp->TOP__v__dmem_controller.dcache__DOT____Vcellout__multip_banks__thread_track_banks),16);
	vcdp->chgBus  (c+167,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank),8);
	vcdp->chgBus  (c+168,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__use_mask_per_bank),16);
	vcdp->chgBus  (c+169,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__valid_per_bank),4);
	vcdp->chgBus  (c+170,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__threads_serviced_per_bank),16);
	vcdp->chgArray(c+171,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__readdata_per_bank),128);
	vcdp->chgBus  (c+175,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__hit_per_bank),4);
	vcdp->chgBus  (c+176,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__eviction_wb),4);
	vcdp->chgBus  (c+177,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_state),4);
	vcdp->chgBus  (c+178,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__use_valid),4);
	vcdp->chgBus  (c+179,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_stored_valid),4);
	vcdp->chgArray(c+180,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__eviction_addr_per_bank),128);
	vcdp->chgBit  (c+184,((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_valid))));
	vcdp->chgBus  (c+185,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__threads_serviced_Qual),4);
	vcdp->chgBus  (c+186,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__debug_hit_per_bank_mask[0]),4);
	vcdp->chgBus  (c+187,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__debug_hit_per_bank_mask[1]),4);
	vcdp->chgBus  (c+188,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__debug_hit_per_bank_mask[2]),4);
	vcdp->chgBus  (c+189,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__debug_hit_per_bank_mask[3]),4);
	vcdp->chgBus  (c+190,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__detect_bank_miss),4);
	vcdp->chgBus  (c+191,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__miss_bank_index),2);
	vcdp->chgBit  (c+192,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__miss_found));
	vcdp->chgBus  (c+193,((0xfU & (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT____Vcellout__multip_banks__thread_track_banks))),4);
	vcdp->chgBus  (c+194,((3U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank))),2);
	vcdp->chgBit  (c+195,((1U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__hit_per_bank))));
	vcdp->chgBus  (c+196,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__readdata_per_bank[0U]),32);
	vcdp->chgBus  (c+197,((0xfU & ((IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT____Vcellout__multip_banks__thread_track_banks) 
				       >> 4U))),4);
	vcdp->chgBus  (c+198,((3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
				     >> 2U))),2);
	vcdp->chgBit  (c+199,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__hit_per_bank) 
				     >> 1U))));
	vcdp->chgBus  (c+200,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__readdata_per_bank[1U]),32);
	vcdp->chgBus  (c+201,((0xfU & ((IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT____Vcellout__multip_banks__thread_track_banks) 
				       >> 8U))),4);
	vcdp->chgBus  (c+202,((3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
				     >> 4U))),2);
	vcdp->chgBit  (c+203,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__hit_per_bank) 
				     >> 2U))));
	vcdp->chgBus  (c+204,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__readdata_per_bank[2U]),32);
	vcdp->chgBus  (c+205,((0xfU & ((IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT____Vcellout__multip_banks__thread_track_banks) 
				       >> 0xcU))),4);
	vcdp->chgBus  (c+206,((3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
				     >> 6U))),2);
	vcdp->chgBit  (c+207,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__hit_per_bank) 
				     >> 3U))));
	vcdp->chgBus  (c+208,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__readdata_per_bank[3U]),32);
	vcdp->chgBus  (c+209,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32);
	vcdp->chgBus  (c+210,((3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2);
	vcdp->chgBit  (c+212,((1U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__valid_per_bank))));
	vcdp->chgBus  (c+214,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32);
	vcdp->chgBus  (c+215,((3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2);
	vcdp->chgBit  (c+217,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__valid_per_bank) 
				     >> 1U))));
	vcdp->chgBus  (c+219,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32);
	vcdp->chgBus  (c+220,((3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2);
	vcdp->chgBit  (c+222,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__valid_per_bank) 
				     >> 2U))));
	vcdp->chgBus  (c+224,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32);
	vcdp->chgBus  (c+225,((3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2);
	vcdp->chgBit  (c+227,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__valid_per_bank) 
				     >> 3U))));
	vcdp->chgBus  (c+229,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__get_miss_index__DOT__i),32);
	vcdp->chgBus  (c+230,((0xfU & ((IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)
				        ? ((IData)(1U) 
					   << (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index))
				        : 0U))),4);
	vcdp->chgBus  (c+231,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),2);
	vcdp->chgBit  (c+232,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found));
	vcdp->chgBus  (c+233,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i),32);
	vcdp->chgBus  (c+234,((0xfU & ((IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)
				        ? ((IData)(1U) 
					   << (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index))
				        : 0U))),4);
	vcdp->chgBus  (c+235,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index),2);
	vcdp->chgBit  (c+236,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found));
	vcdp->chgBus  (c+237,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i),32);
	vcdp->chgBus  (c+238,((0xfU & ((IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)
				        ? ((IData)(1U) 
					   << (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index))
				        : 0U))),4);
	vcdp->chgBus  (c+239,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index),2);
	vcdp->chgBit  (c+240,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found));
	vcdp->chgBus  (c+241,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i),32);
	vcdp->chgBus  (c+242,((0xfU & ((IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)
				        ? ((IData)(1U) 
					   << (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index))
				        : 0U))),4);
	vcdp->chgBus  (c+243,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index),2);
	vcdp->chgBit  (c+244,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found));
	vcdp->chgBus  (c+245,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i),32);
	__Vtemp384[0U] = 0U;
	__Vtemp384[1U] = 0U;
	__Vtemp384[2U] = 0U;
	__Vtemp384[3U] = 0U;
	vcdp->chgBus  (c+246,(__Vtemp384[(3U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank))]),32);
	vcdp->chgBus  (c+247,(((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access)
			        ? ((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				    ? ((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				        ? (0xffffff00U 
					   | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				        : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
				    : ((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				        ? ((0x8000U 
					    & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
					    ? (0xffff0000U 
					       | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
					    : (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
				        : ((5U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
					    ? (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
					    : ((4U 
						== (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
					        ? (0xffU 
						   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
					        : vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))
			        : 0U)),32);
	vcdp->chgBit  (c+248,((((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) 
				& (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
				   == (0x1fffffU & 
				       (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
					>> 0xbU)))) 
			       & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use))));
	vcdp->chgBus  (c+249,((vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
			       << 0xbU)),32);
	vcdp->chgBit  (c+255,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use));
	vcdp->chgBit  (c+256,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access));
	vcdp->chgBit  (c+257,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem));
	vcdp->chgBit  (c+258,((((vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
				 != (0x1fffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
						  >> 0xbU))) 
				& (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)) 
			       & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in))));
	vcdp->chgBit  (c+267,((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+268,((1U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+269,((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+270,((3U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
	vcdp->chgBus  (c+271,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual),32);
	vcdp->chgBus  (c+272,(((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
			        ? (0xffffff00U | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
			        : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32);
	vcdp->chgBus  (c+273,(((0x8000U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
			        ? (0xffff0000U | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
			        : (0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32);
	vcdp->chgBus  (c+274,((0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32);
	vcdp->chgBus  (c+275,((0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32);
	__Vtemp385[0U] = 0U;
	__Vtemp385[1U] = 0U;
	__Vtemp385[2U] = 0U;
	__Vtemp385[3U] = 0U;
	__Vtemp386[0U] = 0U;
	__Vtemp386[1U] = 0U;
	__Vtemp386[2U] = 0U;
	__Vtemp386[3U] = 0U;
	__Vtemp387[0U] = 0U;
	__Vtemp387[1U] = 0U;
	__Vtemp387[2U] = 0U;
	__Vtemp387[3U] = 0U;
	__Vtemp388[0U] = 0U;
	__Vtemp388[1U] = 0U;
	__Vtemp388[2U] = 0U;
	__Vtemp388[3U] = 0U;
	vcdp->chgBus  (c+276,(((1U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
			        ? (0xff00U & (__Vtemp385[
					      (3U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank))] 
					      << 8U))
			        : ((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
				    ? (0xff0000U & 
				       (__Vtemp386[
					(3U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank))] 
					<< 0x10U)) : 
				   ((3U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
				     ? (0xff000000U 
					& (__Vtemp387[
					   (3U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank))] 
					   << 0x18U))
				     : __Vtemp388[(3U 
						   & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank))])))),32);
	__Vtemp389[0U] = 0U;
	__Vtemp389[1U] = 0U;
	__Vtemp389[2U] = 0U;
	__Vtemp389[3U] = 0U;
	__Vtemp390[0U] = 0U;
	__Vtemp390[1U] = 0U;
	__Vtemp390[2U] = 0U;
	__Vtemp390[3U] = 0U;
	vcdp->chgBus  (c+277,(((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
			        ? (0xffff0000U & (__Vtemp389[
						  (3U 
						   & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank))] 
						  << 0x10U))
			        : __Vtemp390[(3U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank))])),32);
	vcdp->chgBus  (c+278,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__use_write_data),32);
	vcdp->chgBus  (c+279,(((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
			        ? ((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				    ? (0xffffff00U 
				       | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				    : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
			        : ((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				    ? ((0x8000U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				        ? (0xffff0000U 
					   | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				        : (0xffffU 
					   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
				    : ((5U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				        ? (0xffffU 
					   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				        : ((4U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
					    ? (0xffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
					    : vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))),32);
	vcdp->chgBus  (c+280,(((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
			        ? 1U : ((1U == (3U 
						& vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
					 ? 2U : ((2U 
						  == 
						  (3U 
						   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
						  ? 4U
						  : 8U)))),4);
	vcdp->chgBus  (c+281,(((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
			        ? 3U : 0xcU)),4);
	vcdp->chgBus  (c+282,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we),16);
	vcdp->chgArray(c+283,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write),128);
	vcdp->chgBit  (c+287,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__genblk1__BRA__0__KET____DOT__normal_write));
	vcdp->chgBit  (c+213,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
	vcdp->chgBus  (c+254,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use),21);
	vcdp->chgArray(c+250,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBus  (c+288,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way),2);
	vcdp->chgBus  (c+289,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way),32);
	vcdp->chgArray(c+290,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way),256);
	vcdp->chgBus  (c+298,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way),2);
	vcdp->chgBus  (c+299,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index),1);
	vcdp->chgBus  (c+300,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual),1);
	vcdp->chgBit  (c+301,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
	vcdp->chgBus  (c+302,((0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)),16);
	vcdp->chgBit  (c+303,((1U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))));
	__Vtemp391[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U];
	__Vtemp391[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U];
	__Vtemp391[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U];
	__Vtemp391[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U];
	vcdp->chgArray(c+304,(__Vtemp391),128);
	vcdp->chgBit  (c+308,((0U != (0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))));
	vcdp->chgBit  (c+309,((1U & ((1U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
				      ? 0U : (0U != 
					      (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))))));
	vcdp->chgBus  (c+310,((0xffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
					  >> 0x10U))),16);
	vcdp->chgBit  (c+311,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
				     >> 1U))));
	__Vtemp392[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U];
	__Vtemp392[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U];
	__Vtemp392[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U];
	__Vtemp392[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U];
	vcdp->chgArray(c+312,(__Vtemp392),128);
	vcdp->chgBus  (c+211,((0x1fffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
					    >> 0xbU))),21);
	vcdp->chgBit  (c+316,((0U != (0xffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						 >> 0x10U)))));
	vcdp->chgBit  (c+317,((1U & ((2U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
				      ? 0U : (0U != 
					      (0xffffU 
					       & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						  >> 0x10U)))))));
	__Vtemp393[0U] = 0U;
	__Vtemp393[1U] = 0U;
	__Vtemp393[2U] = 0U;
	__Vtemp393[3U] = 0U;
	vcdp->chgBus  (c+318,(__Vtemp393[(3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						>> 2U))]),32);
	vcdp->chgBus  (c+319,(((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__access)
			        ? ((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				    ? ((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
				        ? (0xffffff00U 
					   | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
				        : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual))
				    : ((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				        ? ((0x8000U 
					    & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
					    ? (0xffff0000U 
					       | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
					    : (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual))
				        : ((5U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
					    ? (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
					    : ((4U 
						== (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
					        ? (0xffU 
						   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
					        : vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual))))
			        : 0U)),32);
	vcdp->chgBit  (c+320,((((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__access) 
				& (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__tag_use 
				   == (0x1fffffU & 
				       (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
					>> 0xbU)))) 
			       & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__valid_use))));
	vcdp->chgBus  (c+321,((vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__tag_use 
			       << 0xbU)),32);
	vcdp->chgBit  (c+327,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__valid_use));
	vcdp->chgBit  (c+328,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__access));
	vcdp->chgBit  (c+329,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__write_from_mem));
	vcdp->chgBit  (c+330,((((vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__tag_use 
				 != (0x1fffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
						  >> 0xbU))) 
				& (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__valid_use)) 
			       & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in))));
	vcdp->chgBit  (c+331,((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+332,((1U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+333,((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+334,((3U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
	vcdp->chgBus  (c+335,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual),32);
	vcdp->chgBus  (c+336,(((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
			        ? (0xffffff00U | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
			        : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual))),32);
	vcdp->chgBus  (c+337,(((0x8000U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
			        ? (0xffff0000U | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
			        : (0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual))),32);
	vcdp->chgBus  (c+338,((0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)),32);
	vcdp->chgBus  (c+339,((0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)),32);
	__Vtemp394[0U] = 0U;
	__Vtemp394[1U] = 0U;
	__Vtemp394[2U] = 0U;
	__Vtemp394[3U] = 0U;
	__Vtemp395[0U] = 0U;
	__Vtemp395[1U] = 0U;
	__Vtemp395[2U] = 0U;
	__Vtemp395[3U] = 0U;
	__Vtemp396[0U] = 0U;
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	__Vtemp396[2U] = 0U;
	__Vtemp396[3U] = 0U;
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	__Vtemp397[1U] = 0U;
	__Vtemp397[2U] = 0U;
	__Vtemp397[3U] = 0U;
	vcdp->chgBus  (c+340,(((1U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
			        ? (0xff00U & (__Vtemp394[
					      (3U & 
					       ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						>> 2U))] 
					      << 8U))
			        : ((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
				    ? (0xff0000U & 
				       (__Vtemp395[
					(3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
					       >> 2U))] 
					<< 0x10U)) : 
				   ((3U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
				     ? (0xff000000U 
					& (__Vtemp396[
					   (3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						  >> 2U))] 
					   << 0x18U))
				     : __Vtemp397[(3U 
						   & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						      >> 2U))])))),32);
	__Vtemp398[0U] = 0U;
	__Vtemp398[1U] = 0U;
	__Vtemp398[2U] = 0U;
	__Vtemp398[3U] = 0U;
	__Vtemp399[0U] = 0U;
	__Vtemp399[1U] = 0U;
	__Vtemp399[2U] = 0U;
	__Vtemp399[3U] = 0U;
	vcdp->chgBus  (c+341,(((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
			        ? (0xffff0000U & (__Vtemp398[
						  (3U 
						   & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						      >> 2U))] 
						  << 0x10U))
			        : __Vtemp399[(3U & 
					      ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
					       >> 2U))])),32);
	vcdp->chgBus  (c+342,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__use_write_data),32);
	vcdp->chgBus  (c+343,(((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
			        ? ((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
				    ? (0xffffff00U 
				       | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
				    : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual))
			        : ((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				    ? ((0x8000U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
				        ? (0xffff0000U 
					   | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
				        : (0xffffU 
					   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual))
				    : ((5U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				        ? (0xffffU 
					   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
				        : ((4U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
					    ? (0xffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual)
					    : vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_unQual))))),32);
	vcdp->chgBus  (c+344,(((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
			        ? 1U : ((1U == (3U 
						& vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
					 ? 2U : ((2U 
						  == 
						  (3U 
						   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
						  ? 4U
						  : 8U)))),4);
	vcdp->chgBus  (c+345,(((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
			        ? 3U : 0xcU)),4);
	vcdp->chgBus  (c+346,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__we),16);
	vcdp->chgArray(c+347,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_write),128);
	vcdp->chgBit  (c+351,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__genblk1__BRA__0__KET____DOT__normal_write));
	vcdp->chgBit  (c+218,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
	vcdp->chgBus  (c+326,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__tag_use),21);
	vcdp->chgArray(c+322,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBus  (c+352,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way),2);
	vcdp->chgBus  (c+353,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way),32);
	vcdp->chgArray(c+354,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way),256);
	vcdp->chgBus  (c+362,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way),2);
	vcdp->chgBus  (c+363,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index),1);
	vcdp->chgBus  (c+364,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual),1);
	vcdp->chgBit  (c+365,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
	vcdp->chgBus  (c+366,((0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)),16);
	vcdp->chgBit  (c+367,((1U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))));
	__Vtemp400[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U];
	__Vtemp400[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U];
	__Vtemp400[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U];
	__Vtemp400[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U];
	vcdp->chgArray(c+368,(__Vtemp400),128);
	vcdp->chgBit  (c+372,((0U != (0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))));
	vcdp->chgBit  (c+373,((1U & ((1U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
				      ? 0U : (0U != 
					      (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))))));
	vcdp->chgBus  (c+374,((0xffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
					  >> 0x10U))),16);
	vcdp->chgBit  (c+375,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
				     >> 1U))));
	__Vtemp401[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U];
	__Vtemp401[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U];
	__Vtemp401[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U];
	__Vtemp401[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U];
	vcdp->chgArray(c+376,(__Vtemp401),128);
	vcdp->chgBus  (c+216,((0x1fffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
					    >> 0xbU))),21);
	vcdp->chgBit  (c+380,((0U != (0xffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						 >> 0x10U)))));
	vcdp->chgBit  (c+381,((1U & ((2U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
				      ? 0U : (0U != 
					      (0xffffU 
					       & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						  >> 0x10U)))))));
	__Vtemp402[0U] = 0U;
	__Vtemp402[1U] = 0U;
	__Vtemp402[2U] = 0U;
	__Vtemp402[3U] = 0U;
	vcdp->chgBus  (c+382,(__Vtemp402[(3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						>> 4U))]),32);
	vcdp->chgBus  (c+383,(((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__access)
			        ? ((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				    ? ((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
				        ? (0xffffff00U 
					   | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
				        : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual))
				    : ((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				        ? ((0x8000U 
					    & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
					    ? (0xffff0000U 
					       | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
					    : (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual))
				        : ((5U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
					    ? (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
					    : ((4U 
						== (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
					        ? (0xffU 
						   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
					        : vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual))))
			        : 0U)),32);
	vcdp->chgBit  (c+384,((((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__access) 
				& (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__tag_use 
				   == (0x1fffffU & 
				       (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
					>> 0xbU)))) 
			       & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__valid_use))));
	vcdp->chgBus  (c+385,((vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__tag_use 
			       << 0xbU)),32);
	vcdp->chgBit  (c+391,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__valid_use));
	vcdp->chgBit  (c+392,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__access));
	vcdp->chgBit  (c+393,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__write_from_mem));
	vcdp->chgBit  (c+394,((((vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__tag_use 
				 != (0x1fffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
						  >> 0xbU))) 
				& (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__valid_use)) 
			       & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in))));
	vcdp->chgBit  (c+395,((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+396,((1U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+397,((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+398,((3U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
	vcdp->chgBus  (c+399,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual),32);
	vcdp->chgBus  (c+400,(((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
			        ? (0xffffff00U | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
			        : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual))),32);
	vcdp->chgBus  (c+401,(((0x8000U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
			        ? (0xffff0000U | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
			        : (0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual))),32);
	vcdp->chgBus  (c+402,((0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)),32);
	vcdp->chgBus  (c+403,((0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)),32);
	__Vtemp403[0U] = 0U;
	__Vtemp403[1U] = 0U;
	__Vtemp403[2U] = 0U;
	__Vtemp403[3U] = 0U;
	__Vtemp404[0U] = 0U;
	__Vtemp404[1U] = 0U;
	__Vtemp404[2U] = 0U;
	__Vtemp404[3U] = 0U;
	__Vtemp405[0U] = 0U;
	__Vtemp405[1U] = 0U;
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	__Vtemp405[3U] = 0U;
	__Vtemp406[0U] = 0U;
	__Vtemp406[1U] = 0U;
	__Vtemp406[2U] = 0U;
	__Vtemp406[3U] = 0U;
	vcdp->chgBus  (c+404,(((1U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
			        ? (0xff00U & (__Vtemp403[
					      (3U & 
					       ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						>> 4U))] 
					      << 8U))
			        : ((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
				    ? (0xff0000U & 
				       (__Vtemp404[
					(3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
					       >> 4U))] 
					<< 0x10U)) : 
				   ((3U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
				     ? (0xff000000U 
					& (__Vtemp405[
					   (3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						  >> 4U))] 
					   << 0x18U))
				     : __Vtemp406[(3U 
						   & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						      >> 4U))])))),32);
	__Vtemp407[0U] = 0U;
	__Vtemp407[1U] = 0U;
	__Vtemp407[2U] = 0U;
	__Vtemp407[3U] = 0U;
	__Vtemp408[0U] = 0U;
	__Vtemp408[1U] = 0U;
	__Vtemp408[2U] = 0U;
	__Vtemp408[3U] = 0U;
	vcdp->chgBus  (c+405,(((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
			        ? (0xffff0000U & (__Vtemp407[
						  (3U 
						   & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						      >> 4U))] 
						  << 0x10U))
			        : __Vtemp408[(3U & 
					      ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
					       >> 4U))])),32);
	vcdp->chgBus  (c+406,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__use_write_data),32);
	vcdp->chgBus  (c+407,(((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
			        ? ((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
				    ? (0xffffff00U 
				       | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
				    : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual))
			        : ((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				    ? ((0x8000U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
				        ? (0xffff0000U 
					   | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
				        : (0xffffU 
					   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual))
				    : ((5U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				        ? (0xffffU 
					   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
				        : ((4U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
					    ? (0xffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual)
					    : vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_unQual))))),32);
	vcdp->chgBus  (c+408,(((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
			        ? 1U : ((1U == (3U 
						& vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
					 ? 2U : ((2U 
						  == 
						  (3U 
						   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
						  ? 4U
						  : 8U)))),4);
	vcdp->chgBus  (c+409,(((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
			        ? 3U : 0xcU)),4);
	vcdp->chgBus  (c+410,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__we),16);
	vcdp->chgArray(c+411,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_write),128);
	vcdp->chgBit  (c+415,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__genblk1__BRA__0__KET____DOT__normal_write));
	vcdp->chgBit  (c+223,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
	vcdp->chgBus  (c+390,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__tag_use),21);
	vcdp->chgArray(c+386,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBus  (c+416,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way),2);
	vcdp->chgBus  (c+417,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way),32);
	vcdp->chgArray(c+418,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way),256);
	vcdp->chgBus  (c+426,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way),2);
	vcdp->chgBus  (c+427,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index),1);
	vcdp->chgBus  (c+428,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual),1);
	vcdp->chgBit  (c+429,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
	vcdp->chgBus  (c+430,((0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)),16);
	vcdp->chgBit  (c+431,((1U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))));
	__Vtemp409[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U];
	__Vtemp409[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U];
	__Vtemp409[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U];
	__Vtemp409[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U];
	vcdp->chgArray(c+432,(__Vtemp409),128);
	vcdp->chgBit  (c+436,((0U != (0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))));
	vcdp->chgBit  (c+437,((1U & ((1U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
				      ? 0U : (0U != 
					      (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))))));
	vcdp->chgBus  (c+438,((0xffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
					  >> 0x10U))),16);
	vcdp->chgBit  (c+439,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
				     >> 1U))));
	__Vtemp410[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U];
	__Vtemp410[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U];
	__Vtemp410[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U];
	__Vtemp410[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U];
	vcdp->chgArray(c+440,(__Vtemp410),128);
	vcdp->chgBus  (c+221,((0x1fffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
					    >> 0xbU))),21);
	vcdp->chgBit  (c+444,((0U != (0xffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						 >> 0x10U)))));
	vcdp->chgBit  (c+445,((1U & ((2U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
				      ? 0U : (0U != 
					      (0xffffU 
					       & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						  >> 0x10U)))))));
	__Vtemp411[0U] = 0U;
	__Vtemp411[1U] = 0U;
	__Vtemp411[2U] = 0U;
	__Vtemp411[3U] = 0U;
	vcdp->chgBus  (c+446,(__Vtemp411[(3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						>> 6U))]),32);
	vcdp->chgBit  (c+4,(vlSymsp->TOP__v__dmem_controller.__PVT__read_or_write));
	vcdp->chgBus  (c+9,(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read),3);
	vcdp->chgBus  (c+10,(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_write),3);
	vcdp->chgBus  (c+447,(((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__access)
			        ? ((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				    ? ((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
				        ? (0xffffff00U 
					   | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
				        : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual))
				    : ((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				        ? ((0x8000U 
					    & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
					    ? (0xffff0000U 
					       | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
					    : (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual))
				        : ((5U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
					    ? (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
					    : ((4U 
						== (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
					        ? (0xffU 
						   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
					        : vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual))))
			        : 0U)),32);
	vcdp->chgBit  (c+448,((((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__access) 
				& (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__tag_use 
				   == (0x1fffffU & 
				       (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
					>> 0xbU)))) 
			       & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__valid_use))));
	vcdp->chgBus  (c+449,((vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__tag_use 
			       << 0xbU)),32);
	vcdp->chgBit  (c+455,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__valid_use));
	vcdp->chgBit  (c+456,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__access));
	vcdp->chgBit  (c+457,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__write_from_mem));
	vcdp->chgBit  (c+458,((((vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__tag_use 
				 != (0x1fffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
						  >> 0xbU))) 
				& (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__valid_use)) 
			       & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in))));
	vcdp->chgBit  (c+259,((2U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))));
	vcdp->chgBit  (c+260,((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))));
	vcdp->chgBit  (c+261,((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))));
	vcdp->chgBit  (c+262,((5U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))));
	vcdp->chgBit  (c+263,((4U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))));
	vcdp->chgBit  (c+264,((2U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_write))));
	vcdp->chgBit  (c+265,((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_write))));
	vcdp->chgBit  (c+266,((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_write))));
	vcdp->chgBit  (c+459,((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+460,((1U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+461,((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+462,((3U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
	vcdp->chgBus  (c+463,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual),32);
	vcdp->chgBus  (c+464,(((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
			        ? (0xffffff00U | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
			        : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual))),32);
	vcdp->chgBus  (c+465,(((0x8000U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
			        ? (0xffff0000U | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
			        : (0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual))),32);
	vcdp->chgBus  (c+466,((0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)),32);
	vcdp->chgBus  (c+467,((0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)),32);
	__Vtemp412[0U] = 0U;
	__Vtemp412[1U] = 0U;
	__Vtemp412[2U] = 0U;
	__Vtemp412[3U] = 0U;
	__Vtemp413[0U] = 0U;
	__Vtemp413[1U] = 0U;
	__Vtemp413[2U] = 0U;
	__Vtemp413[3U] = 0U;
	__Vtemp414[0U] = 0U;
	__Vtemp414[1U] = 0U;
	__Vtemp414[2U] = 0U;
	__Vtemp414[3U] = 0U;
	__Vtemp415[0U] = 0U;
	__Vtemp415[1U] = 0U;
	__Vtemp415[2U] = 0U;
	__Vtemp415[3U] = 0U;
	vcdp->chgBus  (c+468,(((1U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
			        ? (0xff00U & (__Vtemp412[
					      (3U & 
					       ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						>> 6U))] 
					      << 8U))
			        : ((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
				    ? (0xff0000U & 
				       (__Vtemp413[
					(3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
					       >> 6U))] 
					<< 0x10U)) : 
				   ((3U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
				     ? (0xff000000U 
					& (__Vtemp414[
					   (3U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						  >> 6U))] 
					   << 0x18U))
				     : __Vtemp415[(3U 
						   & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						      >> 6U))])))),32);
	__Vtemp416[0U] = 0U;
	__Vtemp416[1U] = 0U;
	__Vtemp416[2U] = 0U;
	__Vtemp416[3U] = 0U;
	__Vtemp417[0U] = 0U;
	__Vtemp417[1U] = 0U;
	__Vtemp417[2U] = 0U;
	__Vtemp417[3U] = 0U;
	vcdp->chgBus  (c+469,(((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
			        ? (0xffff0000U & (__Vtemp416[
						  (3U 
						   & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
						      >> 6U))] 
						  << 0x10U))
			        : __Vtemp417[(3U & 
					      ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__index_per_bank) 
					       >> 6U))])),32);
	vcdp->chgBus  (c+470,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__use_write_data),32);
	vcdp->chgBus  (c+471,(((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
			        ? ((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
				    ? (0xffffff00U 
				       | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
				    : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual))
			        : ((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				    ? ((0x8000U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
				        ? (0xffff0000U 
					   | vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
				        : (0xffffU 
					   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual))
				    : ((5U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
				        ? (0xffffU 
					   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
				        : ((4U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_mem_read))
					    ? (0xffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual)
					    : vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_unQual))))),32);
	vcdp->chgBus  (c+472,(((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
			        ? 1U : ((1U == (3U 
						& vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
					 ? 2U : ((2U 
						  == 
						  (3U 
						   & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
						  ? 4U
						  : 8U)))),4);
	vcdp->chgBus  (c+473,(((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
			        ? 3U : 0xcU)),4);
	vcdp->chgBus  (c+474,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__we),16);
	vcdp->chgArray(c+475,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_write),128);
	vcdp->chgBit  (c+479,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__genblk1__BRA__0__KET____DOT__normal_write));
	vcdp->chgBit  (c+228,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
	vcdp->chgBus  (c+454,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__tag_use),21);
	vcdp->chgArray(c+450,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBus  (c+480,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way),2);
	vcdp->chgBus  (c+481,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way),32);
	vcdp->chgArray(c+482,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way),256);
	vcdp->chgBus  (c+490,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way),2);
	vcdp->chgBus  (c+491,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index),1);
	vcdp->chgBus  (c+492,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual),1);
	vcdp->chgBit  (c+493,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
	vcdp->chgBus  (c+494,((0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)),16);
	vcdp->chgBit  (c+495,((1U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))));
	__Vtemp418[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U];
	__Vtemp418[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U];
	__Vtemp418[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U];
	__Vtemp418[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U];
	vcdp->chgArray(c+496,(__Vtemp418),128);
	vcdp->chgBit  (c+500,((0U != (0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))));
	vcdp->chgBit  (c+501,((1U & ((1U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
				      ? 0U : (0U != 
					      (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))))));
	vcdp->chgBus  (c+502,((0xffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
					  >> 0x10U))),16);
	vcdp->chgBit  (c+503,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
				     >> 1U))));
	__Vtemp419[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U];
	__Vtemp419[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U];
	__Vtemp419[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U];
	__Vtemp419[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U];
	vcdp->chgArray(c+504,(__Vtemp419),128);
	vcdp->chgBus  (c+226,((0x1fffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
					    >> 0xbU))),21);
	vcdp->chgBit  (c+508,((0U != (0xffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						 >> 0x10U)))));
	vcdp->chgBit  (c+509,((1U & ((2U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
				      ? 0U : (0U != 
					      (0xffffU 
					       & (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						  >> 0x10U)))))));
	vcdp->chgBus  (c+510,((0xfffffff0U & (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
					      << 9U))),32);
	vcdp->chgBus  (c+511,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__new_final_data_read),32);
	vcdp->chgBus  (c+512,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__thread_track_banks),1);
	vcdp->chgBus  (c+514,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__valid_per_bank)
				      ? ((IData)(1U) 
					 << (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__index_per_bank))
				      : 0U))),1);
	vcdp->chgBus  (c+515,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__valid_per_bank),1);
	vcdp->chgBus  (c+516,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__threads_serviced_per_bank),1);
	vcdp->chgBus  (c+518,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__hit_per_bank),1);
	vcdp->chgBus  (c+519,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__new_state),4);
	vcdp->chgBus  (c+520,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__use_valid),1);
	vcdp->chgBus  (c+521,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__new_stored_valid),1);
	vcdp->chgBus  (c+522,((vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
			       << 9U)),32);
	vcdp->chgBus  (c+523,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__threads_serviced_per_bank),1);
	vcdp->chgBus  (c+524,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__debug_hit_per_bank_mask[0]),1);
	vcdp->chgBus  (c+525,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__detect_bank_miss),1);
	vcdp->chgBus  (c+526,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__miss_bank_index),1);
	vcdp->chgBit  (c+527,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__miss_found));
	vcdp->chgBus  (c+528,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__thread_track_banks),1);
	vcdp->chgBus  (c+529,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__index_per_bank),1);
	vcdp->chgBit  (c+530,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__hit_per_bank));
	vcdp->chgBus  (c+531,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32);
	vcdp->chgBus  (c+532,((3U & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2);
	vcdp->chgBit  (c+534,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__valid_per_bank));
	vcdp->chgBus  (c+513,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__index_per_bank),1);
	vcdp->chgBus  (c+23,(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read),3);
	vcdp->chgBus  (c+517,(((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access)
			        ? ((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))
				    ? ((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				        ? (0xffffff00U 
					   | vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				        : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
				    : ((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))
				        ? ((0x8000U 
					    & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
					    ? (0xffff0000U 
					       | vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
					    : (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
				        : ((5U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))
					    ? (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
					    : ((4U 
						== (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))
					        ? (0xffU 
						   & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
					        : vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))
			        : 0U)),32);
	vcdp->chgBit  (c+538,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use));
	vcdp->chgBit  (c+539,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access));
	vcdp->chgBit  (c+540,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem));
	vcdp->chgBit  (c+541,((((vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
				 != (0x7fffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
						  >> 9U))) 
				& (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)) 
			       & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in))));
	vcdp->chgBit  (c+542,((2U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))));
	vcdp->chgBit  (c+543,((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))));
	vcdp->chgBit  (c+544,((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))));
	vcdp->chgBit  (c+545,((5U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))));
	vcdp->chgBit  (c+546,((4U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))));
	vcdp->chgBit  (c+547,((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+548,((1U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+549,((2U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
	vcdp->chgBit  (c+550,((3U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
	vcdp->chgBus  (c+551,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual),32);
	vcdp->chgBus  (c+552,(((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
			        ? (0xffffff00U | vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
			        : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32);
	vcdp->chgBus  (c+553,(((0x8000U & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
			        ? (0xffff0000U | vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
			        : (0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32);
	vcdp->chgBus  (c+554,((0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32);
	vcdp->chgBus  (c+555,((0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32);
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	vcdp->chgBus  (c+557,(0U),32);
	vcdp->chgBus  (c+536,(0U),32);
	vcdp->chgBus  (c+558,(((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))
			        ? ((0x80U & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				    ? (0xffffff00U 
				       | vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				    : (0xffU & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
			        : ((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))
				    ? ((0x8000U & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				        ? (0xffff0000U 
					   | vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				        : (0xffffU 
					   & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
				    : ((5U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))
				        ? (0xffffU 
					   & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
				        : ((4U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache_driver_in_mem_read))
					    ? (0xffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
					    : vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))),32);
	vcdp->chgBus  (c+559,(((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
			        ? 1U : ((1U == (3U 
						& vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
					 ? 2U : ((2U 
						  == 
						  (3U 
						   & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
						  ? 4U
						  : 8U)))),4);
	vcdp->chgBus  (c+560,(((0U == (3U & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
			        ? 3U : 0xcU)),4);
	vcdp->chgBus  (c+561,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we),16);
	vcdp->chgArray(c+562,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write),128);
	vcdp->chgBit  (c+535,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
	vcdp->chgBus  (c+537,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use),23);
	vcdp->chgBus  (c+566,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way),2);
	vcdp->chgBus  (c+567,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way),32);
	vcdp->chgArray(c+568,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way),256);
	vcdp->chgBus  (c+576,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way),2);
	vcdp->chgBus  (c+577,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index),1);
	vcdp->chgBus  (c+578,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual),1);
	vcdp->chgBit  (c+579,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
	vcdp->chgBus  (c+580,((0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)),16);
	vcdp->chgBit  (c+581,((1U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))));
	__Vtemp420[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U];
	__Vtemp420[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U];
	__Vtemp420[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U];
	__Vtemp420[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U];
	vcdp->chgArray(c+582,(__Vtemp420),128);
	vcdp->chgBit  (c+586,((0U != (0xffffU & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))));
	vcdp->chgBit  (c+587,((1U & ((1U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
				      ? 0U : (0U != 
					      (0xffffU 
					       & vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))))));
	vcdp->chgBus  (c+588,((0xffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
					  >> 0x10U))),16);
	vcdp->chgBit  (c+589,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
				     >> 1U))));
	__Vtemp421[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U];
	__Vtemp421[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U];
	__Vtemp421[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U];
	__Vtemp421[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U];
	vcdp->chgArray(c+590,(__Vtemp421),128);
	vcdp->chgBus  (c+533,((0x7fffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
					    >> 9U))),23);
	vcdp->chgBit  (c+594,((0U != (0xffffU & (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						 >> 0x10U)))));
	vcdp->chgBit  (c+595,((1U & ((2U & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
				      ? 0U : (0U != 
					      (0xffffU 
					       & (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						  >> 0x10U)))))));
	vcdp->chgArray(c+5,(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address),128);
	vcdp->chgBus  (c+596,(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid),4);
	__Vtemp426[0U] = ((0xffU == (0xffU & ((vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[1U] 
					       << 8U) 
					      | (vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[0U] 
						 >> 0x18U))))
			   ? (((~ (IData)((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
			       & (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__orig_in_valid)))
			       ? vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__temp_out_data[0U]
			       : 0U) : vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_final_data_read_Qual[0U]);
	__Vtemp426[1U] = ((0xffU == (0xffU & ((vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[1U] 
					       << 8U) 
					      | (vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[0U] 
						 >> 0x18U))))
			   ? (((~ (IData)((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
			       & (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__orig_in_valid)))
			       ? vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__temp_out_data[1U]
			       : 0U) : vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_final_data_read_Qual[1U]);
	__Vtemp426[2U] = ((0xffU == (0xffU & ((vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[1U] 
					       << 8U) 
					      | (vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[0U] 
						 >> 0x18U))))
			   ? (((~ (IData)((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
			       & (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__orig_in_valid)))
			       ? vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__temp_out_data[2U]
			       : 0U) : vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_final_data_read_Qual[2U]);
	__Vtemp426[3U] = ((0xffU == (0xffU & ((vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[1U] 
					       << 8U) 
					      | (vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[0U] 
						 >> 0x18U))))
			   ? (((~ (IData)((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
			       & (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__orig_in_valid)))
			       ? vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__temp_out_data[3U]
			       : 0U) : vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_final_data_read_Qual[3U]);
	vcdp->chgArray(c+597,(__Vtemp426),128);
    }
}

void Vcache_simX::traceChgThis__3(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    int c=code;
    if (0 && vcdp && c) {}  // Prevent unused
    // Body
    {
	vcdp->chgBit  (c+602,(((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
			       | ((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_stored_valid)) 
				  | (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__state))))));
	vcdp->chgBit  (c+605,((1U & ((~ ((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_stored_valid)) 
					 | (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__state)))) 
				     & (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__cache_driver_in_valid)))));
	vcdp->chgBus  (c+606,(((0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
			        ? ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__orig_in_valid) 
				   & (~ (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual)))
			        : ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) 
				   & (~ (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))))),4);
	vcdp->chgBit  (c+607,(((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__state)) 
			       & (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__eviction_wb)))));
	vcdp->chgBit  (c+603,(((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_stored_valid)) 
			       | (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__state)))));
	vcdp->chgBit  (c+608,(((2U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__state)) 
			       & (0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_state)))));
	vcdp->chgBit  (c+609,((1U & (((~ (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
				      & (0U != (0xffffU 
						& vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) 
				     | (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)))));
	vcdp->chgBit  (c+610,((1U & (((~ (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
				      & (0U != (0xffffU 
						& (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						   >> 0x10U)))) 
				     | ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
					>> 1U)))));
	vcdp->chgBit  (c+611,((1U & (((~ (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
				      & (0U != (0xffffU 
						& vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) 
				     | (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)))));
	vcdp->chgBit  (c+612,((1U & (((~ (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
				      & (0U != (0xffffU 
						& (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						   >> 0x10U)))) 
				     | ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
					>> 1U)))));
	vcdp->chgBit  (c+613,((1U & (((~ (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
				      & (0U != (0xffffU 
						& vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) 
				     | (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)))));
	vcdp->chgBit  (c+614,((1U & (((~ (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
				      & (0U != (0xffffU 
						& (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						   >> 0x10U)))) 
				     | ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
					>> 1U)))));
	vcdp->chgBit  (c+615,((1U & (((~ (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
				      & (0U != (0xffffU 
						& vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) 
				     | (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)))));
	vcdp->chgBit  (c+616,((1U & (((~ (IData)(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
				      & (0U != (0xffffU 
						& (vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						   >> 0x10U)))) 
				     | ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
					>> 1U)))));
	vcdp->chgBit  (c+617,(((2U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__state)) 
			       & (0U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__new_state)))));
	vcdp->chgBit  (c+618,((1U & (((~ (IData)(vlSymsp->TOP__v__dmem_controller.icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
				      & (0U != (0xffffU 
						& vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) 
				     | (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)))));
	vcdp->chgBit  (c+619,((1U & (((~ (IData)(vlSymsp->TOP__v__dmem_controller.icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
				      & (0U != (0xffffU 
						& (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
						   >> 0x10U)))) 
				     | ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
					>> 1U)))));
	vcdp->chgBus  (c+604,(((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__threads_serviced_per_bank)
			        ? vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__new_final_data_read
			        : vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__final_data_read)),32);
	vcdp->chgBit  (c+601,(((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__new_stored_valid) 
			       | (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__state)))));
    }
}

void Vcache_simX::traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    int c=code;
    if (0 && vcdp && c) {}  // Prevent unused
    // Body
    {
	vcdp->chgBit  (c+620,(((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__state)) 
			       & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) 
				  >> (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))));
    }
}

void Vcache_simX::traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    int c=code;
    if (0 && vcdp && c) {}  // Prevent unused
    // Variables
    VL_SIGW(__Vtemp427,127,0,4);
    // Body
    {
	vcdp->chgBit  (c+621,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) 
				     >> (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))));
	vcdp->chgBit  (c+622,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) 
				     >> (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))));
	vcdp->chgBit  (c+623,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) 
				     >> (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))));
	vcdp->chgBit  (c+624,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) 
				     >> (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))));
	vcdp->chgBit  (c+629,((1U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) 
				     >> (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))));
	__Vtemp427[0U] = (((0U == (0x1fU & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					    << 7U)))
			    ? 0U : (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
				    ((IData)(1U) + 
				     (4U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					    << 2U)))] 
				    << ((IData)(0x20U) 
					- (0x1fU & 
					   ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					    << 7U))))) 
			  | (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
			     (4U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
				    << 2U))] >> (0x1fU 
						 & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
						    << 7U))));
	__Vtemp427[1U] = (((0U == (0x1fU & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					    << 7U)))
			    ? 0U : (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
				    ((IData)(2U) + 
				     (4U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					    << 2U)))] 
				    << ((IData)(0x20U) 
					- (0x1fU & 
					   ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					    << 7U))))) 
			  | (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
			     ((IData)(1U) + (4U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
						   << 2U)))] 
			     >> (0x1fU & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					  << 7U))));
	__Vtemp427[2U] = (((0U == (0x1fU & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					    << 7U)))
			    ? 0U : (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
				    ((IData)(3U) + 
				     (4U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					    << 2U)))] 
				    << ((IData)(0x20U) 
					- (0x1fU & 
					   ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					    << 7U))))) 
			  | (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
			     ((IData)(2U) + (4U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
						   << 2U)))] 
			     >> (0x1fU & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					  << 7U))));
	__Vtemp427[3U] = (((0U == (0x1fU & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					    << 7U)))
			    ? 0U : (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
				    ((IData)(4U) + 
				     (4U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					    << 2U)))] 
				    << ((IData)(0x20U) 
					- (0x1fU & 
					   ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					    << 7U))))) 
			  | (vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
			     ((IData)(3U) + (4U & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
						   << 2U)))] 
			     >> (0x1fU & ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
					  << 7U))));
	vcdp->chgArray(c+625,(__Vtemp427),128);
    }
}

void Vcache_simX::traceChgThis__6(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    int c=code;
    if (0 && vcdp && c) {}  // Prevent unused
    // Body
    {
	vcdp->chgBus  (c+630,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update),1);
	vcdp->chgBus  (c+631,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__tag_use),21);
	vcdp->chgArray(c+632,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBit  (c+636,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__valid_use));
	vcdp->chgBit  (c+637,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
	vcdp->chgBus  (c+638,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__tag_use),21);
	vcdp->chgArray(c+639,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBit  (c+643,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__valid_use));
	vcdp->chgBit  (c+644,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
	vcdp->chgBus  (c+645,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__way_to_update),1);
	vcdp->chgBus  (c+646,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__tag_use),21);
	vcdp->chgArray(c+647,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBit  (c+651,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__valid_use));
	vcdp->chgBit  (c+652,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
	vcdp->chgBus  (c+653,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__tag_use),21);
	vcdp->chgArray(c+654,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBit  (c+658,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__valid_use));
	vcdp->chgBit  (c+659,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
	vcdp->chgBus  (c+660,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__way_to_update),1);
	vcdp->chgBus  (c+661,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__tag_use),21);
	vcdp->chgArray(c+662,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBit  (c+666,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__valid_use));
	vcdp->chgBit  (c+667,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
	vcdp->chgBus  (c+668,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__tag_use),21);
	vcdp->chgArray(c+669,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBit  (c+673,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__valid_use));
	vcdp->chgBit  (c+674,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
	vcdp->chgBus  (c+675,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__way_to_update),1);
	vcdp->chgBus  (c+676,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__tag_use),21);
	vcdp->chgArray(c+677,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBit  (c+681,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__valid_use));
	vcdp->chgBit  (c+682,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
	vcdp->chgBus  (c+683,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__tag_use),21);
	vcdp->chgArray(c+684,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBit  (c+688,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__valid_use));
	vcdp->chgBit  (c+689,(vlSymsp->TOP__v__dmem_controller.dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
	vcdp->chgBus  (c+690,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update),1);
	vcdp->chgBus  (c+691,(vlSymsp->TOP__v__dmem_controller.icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__tag_use),23);
	vcdp->chgArray(c+692,(vlSymsp->TOP__v__dmem_controller.icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBit  (c+696,(vlSymsp->TOP__v__dmem_controller.icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__valid_use));
	vcdp->chgBit  (c+697,(vlSymsp->TOP__v__dmem_controller.icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
	vcdp->chgBus  (c+698,(vlSymsp->TOP__v__dmem_controller.icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__tag_use),23);
	vcdp->chgArray(c+699,(vlSymsp->TOP__v__dmem_controller.icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__data_use),128);
	vcdp->chgBit  (c+703,(vlSymsp->TOP__v__dmem_controller.icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__valid_use));
	vcdp->chgBit  (c+704,(vlSymsp->TOP__v__dmem_controller.icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
    }
}

void Vcache_simX::traceChgThis__7(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    int c=code;
    if (0 && vcdp && c) {}  // Prevent unused
    // Body
    {
	vcdp->chgQuad (c+705,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way),42);
	vcdp->chgArray(c+707,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way),256);
	vcdp->chgBus  (c+715,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way),2);
	vcdp->chgBus  (c+716,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way),2);
	vcdp->chgBit  (c+717,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found));
	vcdp->chgBus  (c+718,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index),1);
	vcdp->chgBus  (c+719,((3U & (~ (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))),2);
	vcdp->chgQuad (c+720,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way),42);
	vcdp->chgArray(c+722,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way),256);
	vcdp->chgBus  (c+730,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way),2);
	vcdp->chgBus  (c+731,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way),2);
	vcdp->chgBit  (c+732,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found));
	vcdp->chgBus  (c+733,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index),1);
	vcdp->chgBus  (c+734,((3U & (~ (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))),2);
	vcdp->chgQuad (c+735,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way),42);
	vcdp->chgArray(c+737,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way),256);
	vcdp->chgBus  (c+745,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way),2);
	vcdp->chgBus  (c+746,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way),2);
	vcdp->chgBit  (c+747,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found));
	vcdp->chgBus  (c+748,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index),1);
	vcdp->chgBus  (c+749,((3U & (~ (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))),2);
	vcdp->chgQuad (c+750,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way),42);
	vcdp->chgArray(c+752,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way),256);
	vcdp->chgBus  (c+760,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way),2);
	vcdp->chgBus  (c+761,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way),2);
	vcdp->chgBit  (c+762,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found));
	vcdp->chgBus  (c+763,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index),1);
	vcdp->chgBus  (c+764,((3U & (~ (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))),2);
	vcdp->chgQuad (c+765,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way),46);
	vcdp->chgArray(c+767,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way),256);
	vcdp->chgBus  (c+775,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way),2);
	vcdp->chgBus  (c+776,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way),2);
	vcdp->chgBit  (c+777,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found));
	vcdp->chgBus  (c+778,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index),1);
	vcdp->chgBus  (c+779,((3U & (~ (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))),2);
    }
}

void Vcache_simX::traceChgThis__8(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    int c=code;
    if (0 && vcdp && c) {}  // Prevent unused
    // Variables
    VL_SIGW(__Vtemp428,127,0,4);
    VL_SIGW(__Vtemp429,127,0,4);
    VL_SIGW(__Vtemp430,127,0,4);
    VL_SIGW(__Vtemp431,127,0,4);
    VL_SIGW(__Vtemp432,127,0,4);
    VL_SIGW(__Vtemp433,127,0,4);
    VL_SIGW(__Vtemp434,127,0,4);
    VL_SIGW(__Vtemp435,127,0,4);
    VL_SIGW(__Vtemp436,127,0,4);
    VL_SIGW(__Vtemp437,127,0,4);
    VL_SIGW(__Vtemp438,127,0,4);
    VL_SIGW(__Vtemp439,127,0,4);
    VL_SIGW(__Vtemp440,127,0,4);
    VL_SIGW(__Vtemp441,127,0,4);
    VL_SIGW(__Vtemp442,127,0,4);
    VL_SIGW(__Vtemp443,127,0,4);
    VL_SIGW(__Vtemp444,127,0,4);
    VL_SIGW(__Vtemp445,127,0,4);
    VL_SIGW(__Vtemp446,127,0,4);
    VL_SIGW(__Vtemp447,127,0,4);
    VL_SIGW(__Vtemp448,127,0,4);
    VL_SIGW(__Vtemp449,127,0,4);
    VL_SIGW(__Vtemp450,127,0,4);
    VL_SIGW(__Vtemp451,127,0,4);
    VL_SIGW(__Vtemp452,127,0,4);
    VL_SIGW(__Vtemp453,127,0,4);
    VL_SIGW(__Vtemp454,127,0,4);
    VL_SIGW(__Vtemp455,127,0,4);
    VL_SIGW(__Vtemp456,127,0,4);
    VL_SIGW(__Vtemp457,127,0,4);
    VL_SIGW(__Vtemp458,127,0,4);
    VL_SIGW(__Vtemp459,127,0,4);
    VL_SIGW(__Vtemp460,127,0,4);
    VL_SIGW(__Vtemp461,127,0,4);
    VL_SIGW(__Vtemp462,127,0,4);
    VL_SIGW(__Vtemp463,127,0,4);
    VL_SIGW(__Vtemp464,127,0,4);
    VL_SIGW(__Vtemp465,127,0,4);
    VL_SIGW(__Vtemp466,127,0,4);
    VL_SIGW(__Vtemp467,127,0,4);
    VL_SIGW(__Vtemp468,127,0,4);
    VL_SIGW(__Vtemp469,127,0,4);
    VL_SIGW(__Vtemp470,127,0,4);
    VL_SIGW(__Vtemp471,127,0,4);
    VL_SIGW(__Vtemp472,127,0,4);
    VL_SIGW(__Vtemp473,127,0,4);
    VL_SIGW(__Vtemp474,127,0,4);
    VL_SIGW(__Vtemp475,127,0,4);
    VL_SIGW(__Vtemp476,127,0,4);
    VL_SIGW(__Vtemp477,127,0,4);
    VL_SIGW(__Vtemp478,127,0,4);
    VL_SIGW(__Vtemp479,127,0,4);
    VL_SIGW(__Vtemp480,127,0,4);
    VL_SIGW(__Vtemp481,127,0,4);
    VL_SIGW(__Vtemp482,127,0,4);
    VL_SIGW(__Vtemp483,127,0,4);
    VL_SIGW(__Vtemp484,127,0,4);
    VL_SIGW(__Vtemp485,127,0,4);
    VL_SIGW(__Vtemp486,127,0,4);
    VL_SIGW(__Vtemp487,127,0,4);
    VL_SIGW(__Vtemp488,127,0,4);
    VL_SIGW(__Vtemp489,127,0,4);
    VL_SIGW(__Vtemp490,127,0,4);
    VL_SIGW(__Vtemp491,127,0,4);
    VL_SIGW(__Vtemp492,127,0,4);
    VL_SIGW(__Vtemp493,127,0,4);
    VL_SIGW(__Vtemp494,127,0,4);
    VL_SIGW(__Vtemp495,127,0,4);
    VL_SIGW(__Vtemp496,127,0,4);
    VL_SIGW(__Vtemp497,127,0,4);
    VL_SIGW(__Vtemp498,127,0,4);
    VL_SIGW(__Vtemp499,127,0,4);
    VL_SIGW(__Vtemp500,127,0,4);
    VL_SIGW(__Vtemp501,127,0,4);
    VL_SIGW(__Vtemp502,127,0,4);
    VL_SIGW(__Vtemp503,127,0,4);
    VL_SIGW(__Vtemp504,127,0,4);
    VL_SIGW(__Vtemp505,127,0,4);
    VL_SIGW(__Vtemp506,127,0,4);
    VL_SIGW(__Vtemp507,127,0,4);
    VL_SIGW(__Vtemp508,127,0,4);
    VL_SIGW(__Vtemp509,127,0,4);
    VL_SIGW(__Vtemp510,127,0,4);
    VL_SIGW(__Vtemp511,127,0,4);
    VL_SIGW(__Vtemp512,127,0,4);
    VL_SIGW(__Vtemp513,127,0,4);
    VL_SIGW(__Vtemp514,127,0,4);
    VL_SIGW(__Vtemp515,127,0,4);
    VL_SIGW(__Vtemp516,127,0,4);
    VL_SIGW(__Vtemp517,127,0,4);
    VL_SIGW(__Vtemp518,127,0,4);
    VL_SIGW(__Vtemp519,127,0,4);
    VL_SIGW(__Vtemp520,127,0,4);
    VL_SIGW(__Vtemp521,127,0,4);
    VL_SIGW(__Vtemp522,127,0,4);
    VL_SIGW(__Vtemp523,127,0,4);
    VL_SIGW(__Vtemp524,127,0,4);
    VL_SIGW(__Vtemp525,127,0,4);
    VL_SIGW(__Vtemp526,127,0,4);
    VL_SIGW(__Vtemp527,127,0,4);
    VL_SIGW(__Vtemp528,127,0,4);
    VL_SIGW(__Vtemp529,127,0,4);
    VL_SIGW(__Vtemp530,127,0,4);
    VL_SIGW(__Vtemp531,127,0,4);
    VL_SIGW(__Vtemp532,127,0,4);
    VL_SIGW(__Vtemp533,127,0,4);
    VL_SIGW(__Vtemp534,127,0,4);
    VL_SIGW(__Vtemp535,127,0,4);
    VL_SIGW(__Vtemp536,127,0,4);
    VL_SIGW(__Vtemp537,127,0,4);
    VL_SIGW(__Vtemp538,127,0,4);
    VL_SIGW(__Vtemp539,127,0,4);
    VL_SIGW(__Vtemp540,127,0,4);
    VL_SIGW(__Vtemp541,127,0,4);
    VL_SIGW(__Vtemp542,127,0,4);
    VL_SIGW(__Vtemp543,127,0,4);
    VL_SIGW(__Vtemp544,127,0,4);
    VL_SIGW(__Vtemp545,127,0,4);
    VL_SIGW(__Vtemp546,127,0,4);
    VL_SIGW(__Vtemp547,127,0,4);
    VL_SIGW(__Vtemp548,127,0,4);
    VL_SIGW(__Vtemp549,127,0,4);
    VL_SIGW(__Vtemp550,127,0,4);
    VL_SIGW(__Vtemp551,127,0,4);
    VL_SIGW(__Vtemp552,127,0,4);
    VL_SIGW(__Vtemp553,127,0,4);
    VL_SIGW(__Vtemp554,127,0,4);
    VL_SIGW(__Vtemp555,127,0,4);
    VL_SIGW(__Vtemp556,127,0,4);
    VL_SIGW(__Vtemp557,127,0,4);
    VL_SIGW(__Vtemp558,127,0,4);
    VL_SIGW(__Vtemp559,127,0,4);
    VL_SIGW(__Vtemp560,127,0,4);
    VL_SIGW(__Vtemp561,127,0,4);
    VL_SIGW(__Vtemp562,127,0,4);
    VL_SIGW(__Vtemp563,127,0,4);
    VL_SIGW(__Vtemp564,127,0,4);
    VL_SIGW(__Vtemp565,127,0,4);
    VL_SIGW(__Vtemp566,127,0,4);
    VL_SIGW(__Vtemp567,127,0,4);
    VL_SIGW(__Vtemp568,127,0,4);
    VL_SIGW(__Vtemp569,127,0,4);
    VL_SIGW(__Vtemp570,127,0,4);
    VL_SIGW(__Vtemp571,127,0,4);
    VL_SIGW(__Vtemp572,127,0,4);
    VL_SIGW(__Vtemp573,127,0,4);
    VL_SIGW(__Vtemp574,127,0,4);
    VL_SIGW(__Vtemp575,127,0,4);
    VL_SIGW(__Vtemp576,127,0,4);
    VL_SIGW(__Vtemp577,127,0,4);
    VL_SIGW(__Vtemp578,127,0,4);
    VL_SIGW(__Vtemp579,127,0,4);
    VL_SIGW(__Vtemp580,127,0,4);
    VL_SIGW(__Vtemp581,127,0,4);
    VL_SIGW(__Vtemp582,127,0,4);
    VL_SIGW(__Vtemp583,127,0,4);
    VL_SIGW(__Vtemp584,127,0,4);
    VL_SIGW(__Vtemp585,127,0,4);
    VL_SIGW(__Vtemp586,127,0,4);
    VL_SIGW(__Vtemp587,127,0,4);
    VL_SIGW(__Vtemp588,127,0,4);
    VL_SIGW(__Vtemp589,127,0,4);
    VL_SIGW(__Vtemp590,127,0,4);
    VL_SIGW(__Vtemp591,127,0,4);
    VL_SIGW(__Vtemp592,127,0,4);
    VL_SIGW(__Vtemp593,127,0,4);
    VL_SIGW(__Vtemp594,127,0,4);
    VL_SIGW(__Vtemp595,127,0,4);
    VL_SIGW(__Vtemp596,127,0,4);
    VL_SIGW(__Vtemp597,127,0,4);
    VL_SIGW(__Vtemp598,127,0,4);
    VL_SIGW(__Vtemp599,127,0,4);
    VL_SIGW(__Vtemp600,127,0,4);
    VL_SIGW(__Vtemp601,127,0,4);
    VL_SIGW(__Vtemp602,127,0,4);
    VL_SIGW(__Vtemp603,127,0,4);
    VL_SIGW(__Vtemp604,127,0,4);
    VL_SIGW(__Vtemp605,127,0,4);
    VL_SIGW(__Vtemp606,127,0,4);
    VL_SIGW(__Vtemp607,127,0,4);
    VL_SIGW(__Vtemp608,127,0,4);
    VL_SIGW(__Vtemp609,127,0,4);
    VL_SIGW(__Vtemp610,127,0,4);
    VL_SIGW(__Vtemp611,127,0,4);
    VL_SIGW(__Vtemp612,127,0,4);
    VL_SIGW(__Vtemp613,127,0,4);
    VL_SIGW(__Vtemp614,127,0,4);
    VL_SIGW(__Vtemp615,127,0,4);
    VL_SIGW(__Vtemp616,127,0,4);
    VL_SIGW(__Vtemp617,127,0,4);
    VL_SIGW(__Vtemp618,127,0,4);
    VL_SIGW(__Vtemp619,127,0,4);
    VL_SIGW(__Vtemp620,127,0,4);
    VL_SIGW(__Vtemp621,127,0,4);
    VL_SIGW(__Vtemp622,127,0,4);
    VL_SIGW(__Vtemp623,127,0,4);
    VL_SIGW(__Vtemp624,127,0,4);
    VL_SIGW(__Vtemp625,127,0,4);
    VL_SIGW(__Vtemp626,127,0,4);
    VL_SIGW(__Vtemp627,127,0,4);
    VL_SIGW(__Vtemp628,127,0,4);
    VL_SIGW(__Vtemp629,127,0,4);
    VL_SIGW(__Vtemp630,127,0,4);
    VL_SIGW(__Vtemp631,127,0,4);
    VL_SIGW(__Vtemp632,127,0,4);
    VL_SIGW(__Vtemp633,127,0,4);
    VL_SIGW(__Vtemp634,127,0,4);
    VL_SIGW(__Vtemp635,127,0,4);
    VL_SIGW(__Vtemp636,127,0,4);
    VL_SIGW(__Vtemp637,127,0,4);
    VL_SIGW(__Vtemp638,127,0,4);
    VL_SIGW(__Vtemp639,127,0,4);
    VL_SIGW(__Vtemp640,127,0,4);
    VL_SIGW(__Vtemp641,127,0,4);
    VL_SIGW(__Vtemp642,127,0,4);
    VL_SIGW(__Vtemp643,127,0,4);
    VL_SIGW(__Vtemp644,127,0,4);
    VL_SIGW(__Vtemp645,127,0,4);
    VL_SIGW(__Vtemp646,127,0,4);
    VL_SIGW(__Vtemp647,127,0,4);
    VL_SIGW(__Vtemp648,127,0,4);
    VL_SIGW(__Vtemp649,127,0,4);
    VL_SIGW(__Vtemp650,127,0,4);
    VL_SIGW(__Vtemp651,127,0,4);
    VL_SIGW(__Vtemp652,127,0,4);
    VL_SIGW(__Vtemp653,127,0,4);
    VL_SIGW(__Vtemp654,127,0,4);
    VL_SIGW(__Vtemp655,127,0,4);
    VL_SIGW(__Vtemp656,127,0,4);
    VL_SIGW(__Vtemp657,127,0,4);
    VL_SIGW(__Vtemp658,127,0,4);
    VL_SIGW(__Vtemp659,127,0,4);
    VL_SIGW(__Vtemp660,127,0,4);
    VL_SIGW(__Vtemp661,127,0,4);
    VL_SIGW(__Vtemp662,127,0,4);
    VL_SIGW(__Vtemp663,127,0,4);
    VL_SIGW(__Vtemp664,127,0,4);
    VL_SIGW(__Vtemp665,127,0,4);
    VL_SIGW(__Vtemp666,127,0,4);
    VL_SIGW(__Vtemp667,127,0,4);
    VL_SIGW(__Vtemp668,127,0,4);
    VL_SIGW(__Vtemp669,127,0,4);
    VL_SIGW(__Vtemp670,127,0,4);
    VL_SIGW(__Vtemp671,127,0,4);
    VL_SIGW(__Vtemp672,127,0,4);
    VL_SIGW(__Vtemp673,127,0,4);
    VL_SIGW(__Vtemp674,127,0,4);
    VL_SIGW(__Vtemp675,127,0,4);
    VL_SIGW(__Vtemp676,127,0,4);
    VL_SIGW(__Vtemp677,127,0,4);
    VL_SIGW(__Vtemp678,127,0,4);
    VL_SIGW(__Vtemp679,127,0,4);
    VL_SIGW(__Vtemp680,127,0,4);
    VL_SIGW(__Vtemp681,127,0,4);
    VL_SIGW(__Vtemp682,127,0,4);
    VL_SIGW(__Vtemp683,127,0,4);
    VL_SIGW(__Vtemp684,127,0,4);
    VL_SIGW(__Vtemp685,127,0,4);
    VL_SIGW(__Vtemp686,127,0,4);
    VL_SIGW(__Vtemp687,127,0,4);
    VL_SIGW(__Vtemp688,127,0,4);
    VL_SIGW(__Vtemp689,127,0,4);
    VL_SIGW(__Vtemp690,127,0,4);
    VL_SIGW(__Vtemp691,127,0,4);
    VL_SIGW(__Vtemp692,127,0,4);
    VL_SIGW(__Vtemp693,127,0,4);
    VL_SIGW(__Vtemp694,127,0,4);
    VL_SIGW(__Vtemp695,127,0,4);
    VL_SIGW(__Vtemp696,127,0,4);
    VL_SIGW(__Vtemp697,127,0,4);
    VL_SIGW(__Vtemp698,127,0,4);
    VL_SIGW(__Vtemp699,127,0,4);
    VL_SIGW(__Vtemp700,127,0,4);
    VL_SIGW(__Vtemp701,127,0,4);
    VL_SIGW(__Vtemp702,127,0,4);
    VL_SIGW(__Vtemp703,127,0,4);
    VL_SIGW(__Vtemp704,127,0,4);
    VL_SIGW(__Vtemp705,127,0,4);
    VL_SIGW(__Vtemp706,127,0,4);
    VL_SIGW(__Vtemp707,127,0,4);
    VL_SIGW(__Vtemp708,127,0,4);
    VL_SIGW(__Vtemp709,127,0,4);
    VL_SIGW(__Vtemp710,127,0,4);
    VL_SIGW(__Vtemp711,127,0,4);
    VL_SIGW(__Vtemp712,127,0,4);
    VL_SIGW(__Vtemp713,127,0,4);
    VL_SIGW(__Vtemp714,127,0,4);
    VL_SIGW(__Vtemp715,127,0,4);
    VL_SIGW(__Vtemp716,127,0,4);
    VL_SIGW(__Vtemp717,127,0,4);
    VL_SIGW(__Vtemp718,127,0,4);
    VL_SIGW(__Vtemp719,127,0,4);
    VL_SIGW(__Vtemp720,127,0,4);
    VL_SIGW(__Vtemp721,127,0,4);
    VL_SIGW(__Vtemp722,127,0,4);
    VL_SIGW(__Vtemp723,127,0,4);
    VL_SIGW(__Vtemp724,127,0,4);
    VL_SIGW(__Vtemp725,127,0,4);
    VL_SIGW(__Vtemp726,127,0,4);
    VL_SIGW(__Vtemp727,127,0,4);
    VL_SIGW(__Vtemp728,127,0,4);
    VL_SIGW(__Vtemp729,127,0,4);
    VL_SIGW(__Vtemp730,127,0,4);
    VL_SIGW(__Vtemp731,127,0,4);
    VL_SIGW(__Vtemp732,127,0,4);
    VL_SIGW(__Vtemp733,127,0,4);
    VL_SIGW(__Vtemp734,127,0,4);
    VL_SIGW(__Vtemp735,127,0,4);
    VL_SIGW(__Vtemp736,127,0,4);
    VL_SIGW(__Vtemp737,127,0,4);
    VL_SIGW(__Vtemp738,127,0,4);
    VL_SIGW(__Vtemp739,127,0,4);
    VL_SIGW(__Vtemp740,127,0,4);
    VL_SIGW(__Vtemp741,127,0,4);
    VL_SIGW(__Vtemp742,127,0,4);
    VL_SIGW(__Vtemp743,127,0,4);
    VL_SIGW(__Vtemp744,127,0,4);
    VL_SIGW(__Vtemp745,127,0,4);
    VL_SIGW(__Vtemp746,127,0,4);
    VL_SIGW(__Vtemp747,127,0,4);
    // Body
    {
	vcdp->chgBus  (c+782,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests),4);
	vcdp->chgBit  (c+783,((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))));
	vcdp->chgBus  (c+784,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
	vcdp->chgBus  (c+785,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
	vcdp->chgBus  (c+786,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
	vcdp->chgBus  (c+787,(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
	vcdp->chgBus  (c+788,((0xffffffc0U & vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__miss_addr)),32);
	vcdp->chgBit  (c+789,((1U == (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__state))));
	vcdp->chgArray(c+790,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__final_data_read),128);
	vcdp->chgBus  (c+796,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__stored_valid),4);
	vcdp->chgBus  (c+797,(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__miss_addr),32);
	__Vtemp428[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
	    [0U][0U];
	__Vtemp428[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
	    [0U][1U];
	__Vtemp428[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
	    [0U][2U];
	__Vtemp428[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
	    [0U][3U];
	vcdp->chgArray(c+798,(__Vtemp428),128);
	__Vtemp429[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
	    [1U][0U];
	__Vtemp429[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
	    [1U][1U];
	__Vtemp429[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
	    [1U][2U];
	__Vtemp429[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
	    [1U][3U];
	vcdp->chgArray(c+802,(__Vtemp429),128);
	__Vtemp430[0U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
	    [2U][0U];
	__Vtemp430[1U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
	    [2U][1U];
	__Vtemp430[2U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
	    [2U][2U];
	__Vtemp430[3U] = vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
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	vcdp->chgBit  (c+3019,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[20]));
	vcdp->chgBit  (c+3020,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[21]));
	vcdp->chgBit  (c+3021,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[22]));
	vcdp->chgBit  (c+3022,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[23]));
	vcdp->chgBit  (c+3023,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[24]));
	vcdp->chgBit  (c+3024,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[25]));
	vcdp->chgBit  (c+3025,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[26]));
	vcdp->chgBit  (c+3026,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[27]));
	vcdp->chgBit  (c+3027,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[28]));
	vcdp->chgBit  (c+3028,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[29]));
	vcdp->chgBit  (c+3029,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[30]));
	vcdp->chgBit  (c+3030,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[31]));
	vcdp->chgBit  (c+3031,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0]));
	vcdp->chgBit  (c+3032,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[1]));
	vcdp->chgBit  (c+3033,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[2]));
	vcdp->chgBit  (c+3034,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[3]));
	vcdp->chgBit  (c+3035,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[4]));
	vcdp->chgBit  (c+3036,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[5]));
	vcdp->chgBit  (c+3037,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[6]));
	vcdp->chgBit  (c+3038,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[7]));
	vcdp->chgBit  (c+3039,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[8]));
	vcdp->chgBit  (c+3040,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[9]));
	vcdp->chgBit  (c+3041,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[10]));
	vcdp->chgBit  (c+3042,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[11]));
	vcdp->chgBit  (c+3043,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[12]));
	vcdp->chgBit  (c+3044,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[13]));
	vcdp->chgBit  (c+3045,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[14]));
	vcdp->chgBit  (c+3046,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[15]));
	vcdp->chgBit  (c+3047,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[16]));
	vcdp->chgBit  (c+3048,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[17]));
	vcdp->chgBit  (c+3049,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[18]));
	vcdp->chgBit  (c+3050,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[19]));
	vcdp->chgBit  (c+3051,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[20]));
	vcdp->chgBit  (c+3052,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[21]));
	vcdp->chgBit  (c+3053,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[22]));
	vcdp->chgBit  (c+3054,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[23]));
	vcdp->chgBit  (c+3055,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[24]));
	vcdp->chgBit  (c+3056,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[25]));
	vcdp->chgBit  (c+3057,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[26]));
	vcdp->chgBit  (c+3058,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[27]));
	vcdp->chgBit  (c+3059,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[28]));
	vcdp->chgBit  (c+3060,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[29]));
	vcdp->chgBit  (c+3061,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[30]));
	vcdp->chgBit  (c+3062,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[31]));
	vcdp->chgBus  (c+3063,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f),32);
	vcdp->chgBus  (c+3064,(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind),32);
	vcdp->chgBit  (c+781,(vlSymsp->TOP__v.__PVT__dcache_i_m_ready));
	vcdp->chgBit  (c+780,(vlSymsp->TOP__v.__PVT__icache_i_m_ready));
    }
}

void Vcache_simX::traceChgThis__9(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    int c=code;
    if (0 && vcdp && c) {}  // Prevent unused
    // Body
    {
	vcdp->chgBit  (c+3069,(vlTOPp->out_icache_stall));
	vcdp->chgBit  (c+3072,(vlTOPp->in_dcache_in_valid[0]));
	vcdp->chgBit  (c+3073,(vlTOPp->in_dcache_in_valid[1]));
	vcdp->chgBit  (c+3074,(vlTOPp->in_dcache_in_valid[2]));
	vcdp->chgBit  (c+3075,(vlTOPp->in_dcache_in_valid[3]));
	vcdp->chgBus  (c+3076,(vlTOPp->in_dcache_in_address[0]),32);
	vcdp->chgBus  (c+3077,(vlTOPp->in_dcache_in_address[1]),32);
	vcdp->chgBus  (c+3078,(vlTOPp->in_dcache_in_address[2]),32);
	vcdp->chgBus  (c+3079,(vlTOPp->in_dcache_in_address[3]),32);
	vcdp->chgBit  (c+3080,(vlTOPp->out_dcache_stall));
	vcdp->chgBit  (c+3081,(vlSymsp->TOP__v.in_dcache_in_valid[0]));
	vcdp->chgBit  (c+3082,(vlSymsp->TOP__v.in_dcache_in_valid[1]));
	vcdp->chgBit  (c+3083,(vlSymsp->TOP__v.in_dcache_in_valid[2]));
	vcdp->chgBit  (c+3084,(vlSymsp->TOP__v.in_dcache_in_valid[3]));
	vcdp->chgBus  (c+3085,(vlSymsp->TOP__v.in_dcache_in_address[0]),32);
	vcdp->chgBus  (c+3086,(vlSymsp->TOP__v.in_dcache_in_address[1]),32);
	vcdp->chgBus  (c+3087,(vlSymsp->TOP__v.in_dcache_in_address[2]),32);
	vcdp->chgBus  (c+3088,(vlSymsp->TOP__v.in_dcache_in_address[3]),32);
	vcdp->chgBit  (c+3065,(vlTOPp->clk));
	vcdp->chgBit  (c+3066,(vlTOPp->reset));
	vcdp->chgBus  (c+3067,(vlTOPp->in_icache_pc_addr),32);
	vcdp->chgBus  (c+3089,(((IData)(vlTOPp->in_icache_valid_pc_addr)
				 ? 2U : 7U)),3);
	vcdp->chgBit  (c+3068,(vlTOPp->in_icache_valid_pc_addr));
	vcdp->chgBus  (c+3070,(vlTOPp->in_dcache_mem_read),3);
	vcdp->chgBus  (c+3071,(vlTOPp->in_dcache_mem_write),3);
    }
}