DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 ABOUT TO START Warp ID 0 is running ------------------------------------------------------ CYCLE: 5 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000000 help: in PC: 80000000 CUrrent CODE: 597 DEBUG ../core.cpp:703: Fetched at 0x80000000 DEBUG ../core.cpp:704: 0x80000000: auipc; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 80000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000000 wid: 0 rd: 11 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 6 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000000 wid: 0 rd: 11 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 7 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000000 wid: 0 rd: 11 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 8 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000000 wid: 0 rd: 11 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 9 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000000 wid: 0 rd: 11 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000004 help: in PC: 80000004 CUrrent CODE: 6c58593 DEBUG ../core.cpp:703: Fetched at 0x80000004 DEBUG ../core.cpp:704: 0x80000004: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000004 wid: 0 rd: 11 rs1: 11 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 10 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000000 wid: 0 rd: 11 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000004 wid: 0 rd: 11 rs1: 11 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000008 help: in PC: 80000008 CUrrent CODE: 400513 DEBUG ../core.cpp:703: Fetched at 0x80000008 DEBUG ../core.cpp:704: 0x80000008: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000008 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 11 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000000 wid: 0 rd: 11 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000004 wid: 0 rd: 11 rs1: 11 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000008 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x8000000c help: in PC: 8000000c CUrrent CODE: b5106b DEBUG ../core.cpp:703: Fetched at 0x8000000c DEBUG ../core.cpp:704: 0x8000000c: gpgpu; DEBUG ../instruction.cpp:350: Begin instruction execute. WSPAWN DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 8000000c wid: 0 rd: 0 rs1: 10 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 1 stalled: 0 ------------------------------------------------------ CYCLE: 12 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000000 wid: 0 rd: 11 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000004 wid: 0 rd: 11 rs1: 11 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 1 PC: 80000008 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 8000000c wid: 0 rd: 0 rs1: 10 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 1 stalled: 0 ------------------------------------------------------ CYCLE: 13 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000004 wid: 0 rd: 11 rs1: 11 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000008 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000000c wid: 0 rd: 0 rs1: 10 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 1 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[1] DEBUG ../core.cpp:683: in step pc=0x8000006c help: in PC: 8000006c CUrrent CODE: 400513 DEBUG ../core.cpp:703: Fetched at 0x8000006c DEBUG ../core.cpp:704: 0x8000006c: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 8000006c wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 14 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000004 wid: 0 rd: 11 rs1: 11 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000008 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000000c wid: 0 rd: 0 rs1: 10 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 1 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 8000006c wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 15 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000008 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000000c wid: 0 rd: 0 rs1: 10 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 1 stalled: 1 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 8000006c wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 16 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000000c wid: 0 rd: 0 rs1: 10 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 1 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 8000006c wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 17 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000006c wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[1] DEBUG ../core.cpp:683: in step pc=0x8000006c help: in PC: 8000006c CUrrent CODE: 400513 DEBUG ../core.cpp:703: Fetched at 0x8000006c DEBUG ../core.cpp:704: 0x8000006c: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 8000006c wid: 2 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 18 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000006c wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000006c wid: 2 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[1] DEBUG ../core.cpp:683: in step pc=0x8000006c help: in PC: 8000006c CUrrent CODE: 400513 DEBUG ../core.cpp:703: Fetched at 0x8000006c DEBUG ../core.cpp:704: 0x8000006c: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 8000006c wid: 3 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 19 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000006c wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000006c wid: 2 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000006c wid: 3 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000010 help: in PC: 80000010 CUrrent CODE: 5c000ef DEBUG ../core.cpp:703: Fetched at 0x80000010 DEBUG ../core.cpp:704: 0x80000010: jal; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 8000006c DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000010 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 20 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000006c wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000006c wid: 2 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000006c wid: 3 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000010 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 21 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000006c wid: 2 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000006c wid: 3 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000010 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 22 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000006c wid: 3 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000010 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 23 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000010 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[1] DEBUG ../core.cpp:683: in step pc=0x80000070 help: in PC: 80000070 CUrrent CODE: 5006b DEBUG ../core.cpp:703: Fetched at 0x80000070 DEBUG ../core.cpp:704: 0x80000070: gpgpu; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 80000070 wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 24 Stalled Warps: 1 1 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000010 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000070 wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 25 Stalled Warps: 1 1 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000010 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000070 wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 26 Stalled Warps: 1 1 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000010 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000070 wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 27 Stalled Warps: 1 1 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000070 wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[1] DEBUG ../core.cpp:683: in step pc=0x80000070 help: in PC: 80000070 CUrrent CODE: 5006b DEBUG ../core.cpp:703: Fetched at 0x80000070 DEBUG ../core.cpp:704: 0x80000070: gpgpu; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 80000070 wid: 2 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 28 Stalled Warps: 0 1 1 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000070 wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000070 wid: 2 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[1] DEBUG ../core.cpp:683: in step pc=0x80000070 help: in PC: 80000070 CUrrent CODE: 5006b DEBUG ../core.cpp:703: Fetched at 0x80000070 DEBUG ../core.cpp:704: 0x80000070: gpgpu; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 80000070 wid: 3 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 29 Stalled Warps: 0 1 1 1 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000070 wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000070 wid: 2 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000070 wid: 3 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x8000006c help: in PC: 8000006c CUrrent CODE: 400513 DEBUG ../core.cpp:703: Fetched at 0x8000006c DEBUG ../core.cpp:704: 0x8000006c: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 8000006c wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 30 Stalled Warps: 0 1 1 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000070 wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000070 wid: 2 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000070 wid: 3 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000006c wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000070 help: in PC: 80000070 CUrrent CODE: 5006b DEBUG ../core.cpp:703: Fetched at 0x80000070 DEBUG ../core.cpp:704: 0x80000070: gpgpu; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000070 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 31 Stalled Warps: 1 1 1 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000070 wid: 2 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000070 wid: 3 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000006c wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000070 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 32 Stalled Warps: 1 0 1 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000070 wid: 3 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000006c wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000070 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x80000074 help: in PC: 80000074 CUrrent CODE: 1197 DEBUG ../core.cpp:703: Fetched at 0x80000074 DEBUG ../core.cpp:704: 0x80000074: auipc; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001074 80001074 80001074 80001074 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 80000074 wid: 1 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 33 Stalled Warps: 1 0 0 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000006c wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000070 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000074 wid: 1 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 34 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000070 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000074 wid: 1 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x80000074 help: in PC: 80000074 CUrrent CODE: 1197 DEBUG ../core.cpp:703: Fetched at 0x80000074 DEBUG ../core.cpp:704: 0x80000074: auipc; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001074 80001074 80001074 80001074 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 80000074 wid: 2 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 35 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000070 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000074 wid: 1 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000074 wid: 2 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x80000074 help: in PC: 80000074 CUrrent CODE: 1197 DEBUG ../core.cpp:703: Fetched at 0x80000074 DEBUG ../core.cpp:704: 0x80000074: auipc; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001074 80001074 80001074 80001074 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 80000074 wid: 3 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 36 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000074 wid: 1 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000074 wid: 2 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000074 wid: 3 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x80000078 help: in PC: 80000078 CUrrent CODE: 79418193 DEBUG ../core.cpp:703: Fetched at 0x80000078 DEBUG ../core.cpp:704: 0x80000078: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 80000078 wid: 1 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 37 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000074 wid: 1 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000074 wid: 2 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000074 wid: 3 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000078 wid: 1 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x80000078 help: in PC: 80000078 CUrrent CODE: 79418193 DEBUG ../core.cpp:703: Fetched at 0x80000078 DEBUG ../core.cpp:704: 0x80000078: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 80000078 wid: 2 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 38 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000074 wid: 2 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000074 wid: 3 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000078 wid: 1 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000078 wid: 2 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x80000078 help: in PC: 80000078 CUrrent CODE: 79418193 DEBUG ../core.cpp:703: Fetched at 0x80000078 DEBUG ../core.cpp:704: 0x80000078: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 80000078 wid: 3 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 39 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000074 wid: 3 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000078 wid: 1 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000078 wid: 2 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000078 wid: 3 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x80000074 help: in PC: 80000074 CUrrent CODE: 1197 DEBUG ../core.cpp:703: Fetched at 0x80000074 DEBUG ../core.cpp:704: 0x80000074: auipc; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001074 80001074 80001074 80001074 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000074 wid: 0 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 40 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000078 wid: 1 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000078 wid: 2 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000078 wid: 3 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000074 wid: 0 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x8000007c help: in PC: 8000007c CUrrent CODE: 21026f3 DEBUG ../core.cpp:703: Fetched at 0x8000007c DEBUG ../core.cpp:704: 0x8000007c: SYS; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 8000007c wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 41 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000078 wid: 2 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000078 wid: 3 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000074 wid: 0 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000007c wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x8000007c help: in PC: 8000007c CUrrent CODE: 21026f3 DEBUG ../core.cpp:703: Fetched at 0x8000007c DEBUG ../core.cpp:704: 0x8000007c: SYS; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000002 00000002 00000002 00000002 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 8000007c wid: 2 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 42 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000078 wid: 3 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000074 wid: 0 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000007c wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000007c wid: 2 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x8000007c help: in PC: 8000007c CUrrent CODE: 21026f3 DEBUG ../core.cpp:703: Fetched at 0x8000007c DEBUG ../core.cpp:704: 0x8000007c: SYS; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000003 00000003 00000003 00000003 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 8000007c wid: 3 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 43 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000074 wid: 0 rd: 3 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000007c wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000007c wid: 2 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000007c wid: 3 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x80000078 help: in PC: 80000078 CUrrent CODE: 79418193 DEBUG ../core.cpp:703: Fetched at 0x80000078 DEBUG ../core.cpp:704: 0x80000078: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000078 wid: 0 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 44 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000007c wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000007c wid: 2 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000007c wid: 3 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000078 wid: 0 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x80000080 help: in PC: 80000080 CUrrent CODE: 1a69693 DEBUG ../core.cpp:703: Fetched at 0x80000080 DEBUG ../core.cpp:704: 0x80000080: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 80000080 wid: 1 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 45 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000007c wid: 2 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000007c wid: 3 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000078 wid: 0 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000080 wid: 1 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 46 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000007c wid: 3 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000078 wid: 0 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000080 wid: 1 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 47 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000078 wid: 0 rd: 3 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000080 wid: 1 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 48 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000080 wid: 1 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x80000080 help: in PC: 80000080 CUrrent CODE: 1a69693 DEBUG ../core.cpp:703: Fetched at 0x80000080 DEBUG ../core.cpp:704: 0x80000080: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 80000080 wid: 2 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 49 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000080 wid: 1 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000080 wid: 2 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x80000080 help: in PC: 80000080 CUrrent CODE: 1a69693 DEBUG ../core.cpp:703: Fetched at 0x80000080 DEBUG ../core.cpp:704: 0x80000080: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 80000080 wid: 3 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 50 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000080 wid: 1 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000080 wid: 2 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000080 wid: 3 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x8000007c help: in PC: 8000007c CUrrent CODE: 21026f3 DEBUG ../core.cpp:703: Fetched at 0x8000007c DEBUG ../core.cpp:704: 0x8000007c: SYS; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 8000007c wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 51 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000080 wid: 1 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000080 wid: 2 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000080 wid: 3 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000007c wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x80000084 help: in PC: 80000084 CUrrent CODE: 2002673 DEBUG ../core.cpp:703: Fetched at 0x80000084 DEBUG ../core.cpp:704: 0x80000084: SYS; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 80000084 wid: 1 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 52 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000080 wid: 2 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000080 wid: 3 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000007c wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000084 wid: 1 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x80000084 help: in PC: 80000084 CUrrent CODE: 2002673 DEBUG ../core.cpp:703: Fetched at 0x80000084 DEBUG ../core.cpp:704: 0x80000084: SYS; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 80000084 wid: 2 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 53 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000080 wid: 3 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000007c wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000084 wid: 1 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000084 wid: 2 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x80000084 help: in PC: 80000084 CUrrent CODE: 2002673 DEBUG ../core.cpp:703: Fetched at 0x80000084 DEBUG ../core.cpp:704: 0x80000084: SYS; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 80000084 wid: 3 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 54 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000007c wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000084 wid: 1 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000084 wid: 2 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000084 wid: 3 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x80000080 help: in PC: 80000080 CUrrent CODE: 1a69693 DEBUG ../core.cpp:703: Fetched at 0x80000080 DEBUG ../core.cpp:704: 0x80000080: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000080 wid: 0 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 55 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000084 wid: 1 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000084 wid: 2 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000084 wid: 3 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000080 wid: 0 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x80000088 help: in PC: 80000088 CUrrent CODE: a61593 DEBUG ../core.cpp:703: Fetched at 0x80000088 DEBUG ../core.cpp:704: 0x80000088: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 80000088 wid: 1 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 56 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000084 wid: 2 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000084 wid: 3 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000080 wid: 0 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000088 wid: 1 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x80000088 help: in PC: 80000088 CUrrent CODE: a61593 DEBUG ../core.cpp:703: Fetched at 0x80000088 DEBUG ../core.cpp:704: 0x80000088: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 80000088 wid: 2 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 57 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000084 wid: 3 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000080 wid: 0 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000088 wid: 1 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000088 wid: 2 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x80000088 help: in PC: 80000088 CUrrent CODE: a61593 DEBUG ../core.cpp:703: Fetched at 0x80000088 DEBUG ../core.cpp:704: 0x80000088: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 80000088 wid: 3 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 58 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000080 wid: 0 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000088 wid: 1 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000088 wid: 2 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000088 wid: 3 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x80000084 help: in PC: 80000084 CUrrent CODE: 2002673 DEBUG ../core.cpp:703: Fetched at 0x80000084 DEBUG ../core.cpp:704: 0x80000084: SYS; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000084 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 59 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000088 wid: 1 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000088 wid: 2 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000088 wid: 3 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000084 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x8000008c help: in PC: 8000008c CUrrent CODE: 261613 DEBUG ../core.cpp:703: Fetched at 0x8000008c DEBUG ../core.cpp:704: 0x8000008c: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 8000008c wid: 1 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 60 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000088 wid: 2 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000088 wid: 3 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000084 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000008c wid: 1 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x8000008c help: in PC: 8000008c CUrrent CODE: 261613 DEBUG ../core.cpp:703: Fetched at 0x8000008c DEBUG ../core.cpp:704: 0x8000008c: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 8000008c wid: 2 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 61 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000088 wid: 3 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000084 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000008c wid: 1 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000008c wid: 2 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x8000008c help: in PC: 8000008c CUrrent CODE: 261613 DEBUG ../core.cpp:703: Fetched at 0x8000008c DEBUG ../core.cpp:704: 0x8000008c: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 8000008c wid: 3 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 62 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000084 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000008c wid: 1 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000008c wid: 2 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000008c wid: 3 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x80000088 help: in PC: 80000088 CUrrent CODE: a61593 DEBUG ../core.cpp:703: Fetched at 0x80000088 DEBUG ../core.cpp:704: 0x80000088: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000088 wid: 0 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 63 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000008c wid: 1 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000008c wid: 2 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000008c wid: 3 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000088 wid: 0 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x80000090 help: in PC: 80000090 CUrrent CODE: 6ffff137 DEBUG ../core.cpp:703: Fetched at 0x80000090 DEBUG ../core.cpp:704: 0x80000090: lui; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6ffff000 6ffff000 6ffff000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 80000090 wid: 1 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 64 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000008c wid: 2 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000008c wid: 3 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000088 wid: 0 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000090 wid: 1 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 65 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000008c wid: 3 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000088 wid: 0 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000090 wid: 1 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 66 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000088 wid: 0 rd: 11 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000090 wid: 1 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 67 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000090 wid: 1 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x80000090 help: in PC: 80000090 CUrrent CODE: 6ffff137 DEBUG ../core.cpp:703: Fetched at 0x80000090 DEBUG ../core.cpp:704: 0x80000090: lui; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6ffff000 6ffff000 6ffff000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 80000090 wid: 2 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 68 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000090 wid: 1 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000090 wid: 2 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x80000090 help: in PC: 80000090 CUrrent CODE: 6ffff137 DEBUG ../core.cpp:703: Fetched at 0x80000090 DEBUG ../core.cpp:704: 0x80000090: lui; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6ffff000 6ffff000 6ffff000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 80000090 wid: 3 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 69 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000090 wid: 1 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000090 wid: 2 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000090 wid: 3 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x8000008c help: in PC: 8000008c CUrrent CODE: 261613 DEBUG ../core.cpp:703: Fetched at 0x8000008c DEBUG ../core.cpp:704: 0x8000008c: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 8000008c wid: 0 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 70 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000090 wid: 1 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000090 wid: 2 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000090 wid: 3 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000008c wid: 0 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x80000094 help: in PC: 80000094 CUrrent CODE: 40b10133 DEBUG ../core.cpp:703: Fetched at 0x80000094 DEBUG ../core.cpp:704: 0x80000094: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 80000094 wid: 1 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 71 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000090 wid: 2 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000090 wid: 3 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000008c wid: 0 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000094 wid: 1 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x80000094 help: in PC: 80000094 CUrrent CODE: 40b10133 DEBUG ../core.cpp:703: Fetched at 0x80000094 DEBUG ../core.cpp:704: 0x80000094: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 80000094 wid: 2 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 72 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000090 wid: 3 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000008c wid: 0 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000094 wid: 1 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000094 wid: 2 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x80000094 help: in PC: 80000094 CUrrent CODE: 40b10133 DEBUG ../core.cpp:703: Fetched at 0x80000094 DEBUG ../core.cpp:704: 0x80000094: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 80000094 wid: 3 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 73 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000008c wid: 0 rd: 12 rs1: 12 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000094 wid: 1 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000094 wid: 2 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000094 wid: 3 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x80000090 help: in PC: 80000090 CUrrent CODE: 6ffff137 DEBUG ../core.cpp:703: Fetched at 0x80000090 DEBUG ../core.cpp:704: 0x80000090: lui; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6ffff000 6ffff000 6ffff000 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000090 wid: 0 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 74 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000094 wid: 1 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000094 wid: 2 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000094 wid: 3 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000090 wid: 0 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x80000098 help: in PC: 80000098 CUrrent CODE: 40d10133 DEBUG ../core.cpp:703: Fetched at 0x80000098 DEBUG ../core.cpp:704: 0x80000098: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6bfff000 6bffec00 6bffe800 6bffe400 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 80000098 wid: 1 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 75 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000094 wid: 2 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000094 wid: 3 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000090 wid: 0 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000098 wid: 1 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x80000098 help: in PC: 80000098 CUrrent CODE: 40d10133 DEBUG ../core.cpp:703: Fetched at 0x80000098 DEBUG ../core.cpp:704: 0x80000098: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 67fff000 67ffec00 67ffe800 67ffe400 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 80000098 wid: 2 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 76 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000094 wid: 3 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000090 wid: 0 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000098 wid: 1 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000098 wid: 2 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x80000098 help: in PC: 80000098 CUrrent CODE: 40d10133 DEBUG ../core.cpp:703: Fetched at 0x80000098 DEBUG ../core.cpp:704: 0x80000098: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 63fff000 63ffec00 63ffe800 63ffe400 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 80000098 wid: 3 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 77 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000090 wid: 0 rd: 2 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000098 wid: 1 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000098 wid: 2 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000098 wid: 3 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x80000094 help: in PC: 80000094 CUrrent CODE: 40b10133 DEBUG ../core.cpp:703: Fetched at 0x80000094 DEBUG ../core.cpp:704: 0x80000094: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000094 wid: 0 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 78 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000098 wid: 1 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000098 wid: 2 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000098 wid: 3 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000094 wid: 0 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x8000009c help: in PC: 8000009c CUrrent CODE: c10133 DEBUG ../core.cpp:703: Fetched at 0x8000009c DEBUG ../core.cpp:704: 0x8000009c: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 8000009c wid: 1 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 79 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000098 wid: 2 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000098 wid: 3 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000094 wid: 0 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000009c wid: 1 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x8000009c help: in PC: 8000009c CUrrent CODE: c10133 DEBUG ../core.cpp:703: Fetched at 0x8000009c DEBUG ../core.cpp:704: 0x8000009c: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 67fff000 67ffec04 67ffe808 67ffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 8000009c wid: 2 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 80 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000098 wid: 3 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000094 wid: 0 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000009c wid: 1 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000009c wid: 2 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x8000009c help: in PC: 8000009c CUrrent CODE: c10133 DEBUG ../core.cpp:703: Fetched at 0x8000009c DEBUG ../core.cpp:704: 0x8000009c: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 63fff000 63ffec04 63ffe808 63ffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 8000009c wid: 3 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 81 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000094 wid: 0 rd: 2 rs1: 2 rs2: 11 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000009c wid: 1 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000009c wid: 2 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000009c wid: 3 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x80000098 help: in PC: 80000098 CUrrent CODE: 40d10133 DEBUG ../core.cpp:703: Fetched at 0x80000098 DEBUG ../core.cpp:704: 0x80000098: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000098 wid: 0 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 82 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000009c wid: 1 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000009c wid: 2 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000009c wid: 3 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000098 wid: 0 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x800000a0 help: in PC: 800000a0 CUrrent CODE: 21026f3 DEBUG ../core.cpp:703: Fetched at 0x800000a0 DEBUG ../core.cpp:704: 0x800000a0: SYS; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 800000a0 wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 83 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000009c wid: 2 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000009c wid: 3 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000098 wid: 0 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000a0 wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 84 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000009c wid: 3 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000098 wid: 0 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000a0 wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 85 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000098 wid: 0 rd: 2 rs1: 2 rs2: 13 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000a0 wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 86 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000a0 wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x800000a0 help: in PC: 800000a0 CUrrent CODE: 21026f3 DEBUG ../core.cpp:703: Fetched at 0x800000a0 DEBUG ../core.cpp:704: 0x800000a0: SYS; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 67fff000 67ffec04 67ffe808 67ffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000002 00000002 00000002 00000002 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 800000a0 wid: 2 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 87 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000a0 wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000a0 wid: 2 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x800000a0 help: in PC: 800000a0 CUrrent CODE: 21026f3 DEBUG ../core.cpp:703: Fetched at 0x800000a0 DEBUG ../core.cpp:704: 0x800000a0: SYS; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 63fff000 63ffec04 63ffe808 63ffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000003 00000003 00000003 00000003 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 800000a0 wid: 3 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 88 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000a0 wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000a0 wid: 2 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000a0 wid: 3 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x8000009c help: in PC: 8000009c CUrrent CODE: c10133 DEBUG ../core.cpp:703: Fetched at 0x8000009c DEBUG ../core.cpp:704: 0x8000009c: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 8000009c wid: 0 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 89 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000a0 wid: 1 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000a0 wid: 2 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000a0 wid: 3 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000009c wid: 0 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x800000a4 help: in PC: 800000a4 CUrrent CODE: 68663 DEBUG ../core.cpp:703: Fetched at 0x800000a4 DEBUG ../core.cpp:704: 0x800000a4: branch; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 800000a4 wid: 1 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 90 Stalled Warps: 0 1 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000a0 wid: 2 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000a0 wid: 3 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000009c wid: 0 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000a4 wid: 1 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x800000a4 help: in PC: 800000a4 CUrrent CODE: 68663 DEBUG ../core.cpp:703: Fetched at 0x800000a4 DEBUG ../core.cpp:704: 0x800000a4: branch; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 67fff000 67ffec04 67ffe808 67ffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000002 00000002 00000002 00000002 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 800000a4 wid: 2 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 91 Stalled Warps: 0 1 1 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000a0 wid: 3 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000009c wid: 0 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000a4 wid: 1 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000a4 wid: 2 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x800000a4 help: in PC: 800000a4 CUrrent CODE: 68663 DEBUG ../core.cpp:703: Fetched at 0x800000a4 DEBUG ../core.cpp:704: 0x800000a4: branch; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 63fff000 63ffec04 63ffe808 63ffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000003 00000003 00000003 00000003 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 800000a4 wid: 3 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 92 Stalled Warps: 0 1 1 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000009c wid: 0 rd: 2 rs1: 2 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000a4 wid: 1 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000a4 wid: 2 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000a4 wid: 3 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x800000a0 help: in PC: 800000a0 CUrrent CODE: 21026f3 DEBUG ../core.cpp:703: Fetched at 0x800000a0 DEBUG ../core.cpp:704: 0x800000a0: SYS; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000a0 wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 93 Stalled Warps: 0 1 1 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000a4 wid: 1 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000a4 wid: 2 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000a4 wid: 3 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000a0 wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x800000a4 help: in PC: 800000a4 CUrrent CODE: 68663 DEBUG ../core.cpp:703: Fetched at 0x800000a4 DEBUG ../core.cpp:704: 0x800000a4: branch; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 800000b0 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000a4 wid: 0 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 94 Stalled Warps: 1 1 1 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000a4 wid: 2 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000a4 wid: 3 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000a0 wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000a4 wid: 0 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 95 Stalled Warps: 1 0 1 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000a4 wid: 3 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000a0 wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000a4 wid: 0 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x800000a8 help: in PC: 800000a8 CUrrent CODE: 513 DEBUG ../core.cpp:703: Fetched at 0x800000a8 DEBUG ../core.cpp:704: 0x800000a8: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 800000a8 wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 96 Stalled Warps: 1 0 0 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000a0 wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000a4 wid: 0 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000a8 wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 97 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000a4 wid: 0 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000a8 wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x800000a8 help: in PC: 800000a8 CUrrent CODE: 513 DEBUG ../core.cpp:703: Fetched at 0x800000a8 DEBUG ../core.cpp:704: 0x800000a8: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 67fff000 67ffec04 67ffe808 67ffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000002 00000002 00000002 00000002 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 800000a8 wid: 2 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 98 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000a4 wid: 0 rd: -1 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000a8 wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000a8 wid: 2 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x800000a8 help: in PC: 800000a8 CUrrent CODE: 513 DEBUG ../core.cpp:703: Fetched at 0x800000a8 DEBUG ../core.cpp:704: 0x800000a8: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 63fff000 63ffec04 63ffe808 63ffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000003 00000003 00000003 00000003 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 800000a8 wid: 3 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 99 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000a8 wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000a8 wid: 2 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000a8 wid: 3 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 1[4] DEBUG ../core.cpp:683: in step pc=0x800000ac help: in PC: 800000ac CUrrent CODE: 5006b DEBUG ../core.cpp:703: Fetched at 0x800000ac DEBUG ../core.cpp:704: 0x800000ac: gpgpu; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 0 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 0 active threads in 1 ********************************** Fetch ********************************* valid: 1 PC: 800000ac wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 100 Stalled Warps: 0 1 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000a8 wid: 1 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000a8 wid: 2 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000a8 wid: 3 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000ac wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 2[4] DEBUG ../core.cpp:683: in step pc=0x800000ac help: in PC: 800000ac CUrrent CODE: 5006b DEBUG ../core.cpp:703: Fetched at 0x800000ac DEBUG ../core.cpp:704: 0x800000ac: gpgpu; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 67fff000 67ffec04 67ffe808 67ffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000002 00000002 00000002 00000002 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 0 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 0 active threads in 2 ********************************** Fetch ********************************* valid: 1 PC: 800000ac wid: 2 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 101 Stalled Warps: 0 1 1 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000a8 wid: 2 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000a8 wid: 3 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000ac wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000ac wid: 2 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 3[4] DEBUG ../core.cpp:683: in step pc=0x800000ac help: in PC: 800000ac CUrrent CODE: 5006b DEBUG ../core.cpp:703: Fetched at 0x800000ac DEBUG ../core.cpp:704: 0x800000ac: gpgpu; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 63fff000 63ffec04 63ffe808 63ffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000003 00000003 00000003 00000003 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 0 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 0 active threads in 3 ********************************** Fetch ********************************* valid: 1 PC: 800000ac wid: 3 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 102 Stalled Warps: 0 1 1 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000a8 wid: 3 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000ac wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000ac wid: 2 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000ac wid: 3 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x800000b0 help: in PC: 800000b0 CUrrent CODE: 8067 DEBUG ../core.cpp:703: Fetched at 0x800000b0 DEBUG ../core.cpp:704: 0x800000b0: jalr; DEBUG ../instruction.cpp:350: Begin instruction execute. JALR_INST JALR_INST JALR_INST JALR_INST DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000014 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000b0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 103 Stalled Warps: 1 1 1 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000ac wid: 1 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000ac wid: 2 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000ac wid: 3 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000b0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 104 Stalled Warps: 1 1 1 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000ac wid: 2 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000ac wid: 3 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000b0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 105 Stalled Warps: 1 0 1 1 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000ac wid: 3 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000b0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 106 Stalled Warps: 1 0 0 1 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000b0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 107 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000b0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 108 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000b0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 109 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000b0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 110 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 111 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x80000014 help: in PC: 80000014 CUrrent CODE: 100513 DEBUG ../core.cpp:703: Fetched at 0x80000014 DEBUG ../core.cpp:704: 0x80000014: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000014 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 112 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000014 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x80000018 help: in PC: 80000018 CUrrent CODE: 5006b DEBUG ../core.cpp:703: Fetched at 0x80000018 DEBUG ../core.cpp:704: 0x80000018: gpgpu; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000018 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 113 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000014 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000018 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 114 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000014 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000018 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 115 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000014 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000018 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 116 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000018 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 117 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000018 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 118 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 119 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x8000001c help: in PC: 8000001c CUrrent CODE: c3818513 DEBUG ../core.cpp:703: Fetched at 0x8000001c DEBUG ../core.cpp:704: 0x8000001c: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 8000001c wid: 0 rd: 10 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 120 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000001c wid: 0 rd: 10 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000020 help: in PC: 80000020 CUrrent CODE: c3c18613 DEBUG ../core.cpp:703: Fetched at 0x80000020 DEBUG ../core.cpp:704: 0x80000020: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 80001444 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000020 wid: 0 rd: 12 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 121 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000001c wid: 0 rd: 10 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000020 wid: 0 rd: 12 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 122 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000001c wid: 0 rd: 10 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000020 wid: 0 rd: 12 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 123 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000001c wid: 0 rd: 10 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000020 wid: 0 rd: 12 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 124 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000020 wid: 0 rd: 12 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000024 help: in PC: 80000024 CUrrent CODE: 40a60633 DEBUG ../core.cpp:703: Fetched at 0x80000024 DEBUG ../core.cpp:704: 0x80000024: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000024 wid: 0 rd: 12 rs1: 12 rs2: 10 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 125 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000020 wid: 0 rd: 12 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000024 wid: 0 rd: 12 rs1: 12 rs2: 10 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000028 help: in PC: 80000028 CUrrent CODE: 593 DEBUG ../core.cpp:703: Fetched at 0x80000028 DEBUG ../core.cpp:704: 0x80000028: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000028 wid: 0 rd: 11 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 126 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000020 wid: 0 rd: 12 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000024 wid: 0 rd: 12 rs1: 12 rs2: 10 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000028 wid: 0 rd: 11 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x8000002c help: in PC: 8000002c CUrrent CODE: 1f5000ef DEBUG ../core.cpp:703: Fetched at 0x8000002c DEBUG ../core.cpp:704: 0x8000002c: jal; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000a20 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 8000002c wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 127 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000020 wid: 0 rd: 12 rs1: 3 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000024 wid: 0 rd: 12 rs1: 12 rs2: 10 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 1 PC: 80000028 wid: 0 rd: 11 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 8000002c wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 128 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000024 wid: 0 rd: 12 rs1: 12 rs2: 10 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000028 wid: 0 rd: 11 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000002c wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 129 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000024 wid: 0 rd: 12 rs1: 12 rs2: 10 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000028 wid: 0 rd: 11 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000002c wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 130 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000028 wid: 0 rd: 11 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000002c wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 131 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000002c wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 132 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 133 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a20 help: in PC: 80000a20 CUrrent CODE: f00313 DEBUG ../core.cpp:703: Fetched at 0x80000a20 DEBUG ../core.cpp:704: 0x80000a20: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a20 wid: 0 rd: 6 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 134 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a20 wid: 0 rd: 6 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 135 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a20 wid: 0 rd: 6 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 136 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a20 wid: 0 rd: 6 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 137 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a20 wid: 0 rd: 6 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a24 help: in PC: 80000a24 CUrrent CODE: 50713 DEBUG ../core.cpp:703: Fetched at 0x80000a24 DEBUG ../core.cpp:704: 0x80000a24: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a24 wid: 0 rd: 14 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 138 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a20 wid: 0 rd: 6 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a24 wid: 0 rd: 14 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a28 help: in PC: 80000a28 CUrrent CODE: 2c37e63 DEBUG ../core.cpp:703: Fetched at 0x80000a28 DEBUG ../core.cpp:704: 0x80000a28: branch; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000a64 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a28 wid: 0 rd: -1 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 139 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000a20 wid: 0 rd: 6 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a24 wid: 0 rd: 14 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a28 wid: 0 rd: -1 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 140 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a20 wid: 0 rd: 6 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000a24 wid: 0 rd: 14 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a28 wid: 0 rd: -1 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 141 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a24 wid: 0 rd: 14 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000a28 wid: 0 rd: -1 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 142 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a28 wid: 0 rd: -1 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 143 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 144 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a64 help: in PC: 80000a64 CUrrent CODE: 40c306b3 DEBUG ../core.cpp:703: Fetched at 0x80000a64 DEBUG ../core.cpp:704: 0x80000a64: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 0000000b 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a64 wid: 0 rd: 13 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 145 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a64 wid: 0 rd: 13 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 146 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a64 wid: 0 rd: 13 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 147 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a64 wid: 0 rd: 13 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 148 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a64 wid: 0 rd: 13 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a68 help: in PC: 80000a68 CUrrent CODE: 269693 DEBUG ../core.cpp:703: Fetched at 0x80000a68 DEBUG ../core.cpp:704: 0x80000a68: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 0000002c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a68 wid: 0 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 149 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a64 wid: 0 rd: 13 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a68 wid: 0 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a6c help: in PC: 80000a6c CUrrent CODE: 297 DEBUG ../core.cpp:703: Fetched at 0x80000a6c DEBUG ../core.cpp:704: 0x80000a6c: auipc; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 0000002c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a6c wid: 0 rd: 5 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 150 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000a64 wid: 0 rd: 13 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a68 wid: 0 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a6c wid: 0 rd: 5 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a70 help: in PC: 80000a70 CUrrent CODE: 5686b3 DEBUG ../core.cpp:703: Fetched at 0x80000a70 DEBUG ../core.cpp:704: 0x80000a70: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a70 wid: 0 rd: 13 rs1: 13 rs2: 5 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 151 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a64 wid: 0 rd: 13 rs1: 6 rs2: 12 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a68 wid: 0 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 1 PC: 80000a6c wid: 0 rd: 5 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a70 wid: 0 rd: 13 rs1: 13 rs2: 5 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 152 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000a68 wid: 0 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a6c wid: 0 rd: 5 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a70 wid: 0 rd: 13 rs1: 13 rs2: 5 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 153 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a68 wid: 0 rd: 13 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000a6c wid: 0 rd: 5 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a70 wid: 0 rd: 13 rs1: 13 rs2: 5 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 154 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a6c wid: 0 rd: 5 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a70 wid: 0 rd: 13 rs1: 13 rs2: 5 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a74 help: in PC: 80000a74 CUrrent CODE: c68067 DEBUG ../core.cpp:703: Fetched at 0x80000a74 DEBUG ../core.cpp:704: 0x80000a74: jalr; DEBUG ../instruction.cpp:350: Begin instruction execute. JALR_INST DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000aa4 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a74 wid: 0 rd: 0 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 155 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a70 wid: 0 rd: 13 rs1: 13 rs2: 5 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a74 wid: 0 rd: 0 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 156 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000a70 wid: 0 rd: 13 rs1: 13 rs2: 5 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a74 wid: 0 rd: 0 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 157 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a70 wid: 0 rd: 13 rs1: 13 rs2: 5 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a74 wid: 0 rd: 0 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 158 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000a74 wid: 0 rd: 0 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 159 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a74 wid: 0 rd: 0 rs1: 13 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 160 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 161 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000aa4 help: in PC: 80000aa4 CUrrent CODE: b701a3 DEBUG ../core.cpp:703: Fetched at 0x80000aa4 DEBUG ../core.cpp:704: 0x80000aa4: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 80001440 + 3 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000aa4 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 3 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 162 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000aa4 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 2 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 163 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000aa4 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 1 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 164 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000aa4 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 165 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000aa4 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000aa8 help: in PC: 80000aa8 CUrrent CODE: b70123 DEBUG ../core.cpp:703: Fetched at 0x80000aa8 DEBUG ../core.cpp:704: 0x80000aa8: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 80001440 + 2 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000aa8 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 166 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000aa4 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000aa8 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000aac help: in PC: 80000aac CUrrent CODE: b700a3 DEBUG ../core.cpp:703: Fetched at 0x80000aac DEBUG ../core.cpp:704: 0x80000aac: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 80001440 + 1 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000aac wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 167 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000aa4 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 2 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000aa8 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000aac wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000ab0 help: in PC: 80000ab0 CUrrent CODE: b70023 DEBUG ../core.cpp:703: Fetched at 0x80000ab0 DEBUG ../core.cpp:704: 0x80000ab0: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 80001440 + 0 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000ab0 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 168 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000aa8 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000aac wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000ab0 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 169 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000aac wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000ab0 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 170 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000ab0 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 171 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000ab0 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000ab4 help: in PC: 80000ab4 CUrrent CODE: 8067 DEBUG ../core.cpp:703: Fetched at 0x80000ab4 DEBUG ../core.cpp:704: 0x80000ab4: jalr; DEBUG ../instruction.cpp:350: Begin instruction execute. JALR_INST DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000030 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000ab4 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 172 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000ab0 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000ab4 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 173 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000ab0 wid: 0 rd: -1 rs1: 14 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000ab4 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 174 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000ab4 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 175 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000ab4 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 176 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 177 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000030 help: in PC: 80000030 CUrrent CODE: 1517 DEBUG ../core.cpp:703: Fetched at 0x80000030 DEBUG ../core.cpp:704: 0x80000030: auipc; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80001030 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000030 wid: 0 rd: 10 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 178 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000030 wid: 0 rd: 10 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 179 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000030 wid: 0 rd: 10 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 180 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000030 wid: 0 rd: 10 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 181 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000030 wid: 0 rd: 10 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000034 help: in PC: 80000034 CUrrent CODE: 8f450513 DEBUG ../core.cpp:703: Fetched at 0x80000034 DEBUG ../core.cpp:704: 0x80000034: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80000924 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000034 wid: 0 rd: 10 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 182 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000030 wid: 0 rd: 10 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000034 wid: 0 rd: 10 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000038 help: in PC: 80000038 CUrrent CODE: a9000ef DEBUG ../core.cpp:703: Fetched at 0x80000038 DEBUG ../core.cpp:704: 0x80000038: jal; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 800008e0 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80000924 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000038 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 183 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000030 wid: 0 rd: 10 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000034 wid: 0 rd: 10 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000038 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 184 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000030 wid: 0 rd: 10 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000034 wid: 0 rd: 10 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 1 PC: 80000038 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 185 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000034 wid: 0 rd: 10 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000038 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 186 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000034 wid: 0 rd: 10 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000038 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 187 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000038 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 188 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 189 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800008e0 help: in PC: 800008e0 CUrrent CODE: 50593 DEBUG ../core.cpp:703: Fetched at 0x800008e0 DEBUG ../core.cpp:704: 0x800008e0: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80000924 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008e0 wid: 0 rd: 11 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 190 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008e0 wid: 0 rd: 11 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 191 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008e0 wid: 0 rd: 11 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 192 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008e0 wid: 0 rd: 11 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 193 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008e0 wid: 0 rd: 11 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800008e4 help: in PC: 800008e4 CUrrent CODE: 693 DEBUG ../core.cpp:703: Fetched at 0x800008e4 DEBUG ../core.cpp:704: 0x800008e4: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80000924 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008e4 wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 194 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008e0 wid: 0 rd: 11 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008e4 wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800008e8 help: in PC: 800008e8 CUrrent CODE: 613 DEBUG ../core.cpp:703: Fetched at 0x800008e8 DEBUG ../core.cpp:704: 0x800008e8: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 80000924 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008e8 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 195 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800008e0 wid: 0 rd: 11 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008e4 wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008e8 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800008ec help: in PC: 800008ec CUrrent CODE: 513 DEBUG ../core.cpp:703: Fetched at 0x800008ec DEBUG ../core.cpp:704: 0x800008ec: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008ec wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 196 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800008e0 wid: 0 rd: 11 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800008e4 wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008e8 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008ec wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800008f0 help: in PC: 800008f0 CUrrent CODE: 20c0006f DEBUG ../core.cpp:703: Fetched at 0x800008f0 DEBUG ../core.cpp:704: 0x800008f0: jal; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000afc DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008f0 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 197 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800008e4 wid: 0 rd: 13 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800008e8 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008ec wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008f0 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 198 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800008e8 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800008ec wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008f0 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 199 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800008ec wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008f0 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 200 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008f0 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 201 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008f0 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 202 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800008f0 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 203 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800008f0 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 204 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 205 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000afc help: in PC: 80000afc CUrrent CODE: c281a703 DEBUG ../core.cpp:703: Fetched at 0x80000afc DEBUG ../core.cpp:704: 0x80000afc: load; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000afc wid: 0 rd: 14 rs1: 3 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 206 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000afc wid: 0 rd: 14 rs1: 3 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 207 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000afc wid: 0 rd: 14 rs1: 3 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 208 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000afc wid: 0 rd: 14 rs1: 3 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 209 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000afc wid: 0 rd: 14 rs1: 3 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b00 help: in PC: 80000b00 CUrrent CODE: 14872783 DEBUG ../core.cpp:703: Fetched at 0x80000b00 DEBUG ../core.cpp:704: 0x80000b00: load; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b00 wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 210 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000afc wid: 0 rd: 14 rs1: 3 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b00 wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 211 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000afc wid: 0 rd: 14 rs1: 3 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 2 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b00 wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 212 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000afc wid: 0 rd: 14 rs1: 3 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 1 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b00 wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 213 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000afc wid: 0 rd: 14 rs1: 3 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b00 wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b04 help: in PC: 80000b04 CUrrent CODE: 4078c63 DEBUG ../core.cpp:703: Fetched at 0x80000b04 DEBUG ../core.cpp:704: 0x80000b04: branch; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000b5c DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b04 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 214 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000afc wid: 0 rd: 14 rs1: 3 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b00 wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b04 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 215 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000b00 wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 2 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b04 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 216 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000b00 wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 1 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b04 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 217 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000b00 wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b04 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 218 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b00 wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b04 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 219 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000b04 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 220 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b04 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 221 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 222 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b5c help: in PC: 80000b5c CUrrent CODE: 14c70793 DEBUG ../core.cpp:703: Fetched at 0x80000b5c DEBUG ../core.cpp:704: 0x80000b5c: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b5c wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 223 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b5c wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 224 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b5c wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 225 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b5c wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 226 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b5c wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b60 help: in PC: 80000b60 CUrrent CODE: 14f72423 DEBUG ../core.cpp:703: Fetched at 0x80000b60 DEBUG ../core.cpp:704: 0x80000b60: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 80001008 + 148 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b60 wid: 0 rd: -1 rs1: 14 rs2: 15 is_lw: 0 is_sw: 1 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 227 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b5c wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b60 wid: 0 rd: -1 rs1: 14 rs2: 15 is_lw: 0 is_sw: 1 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 228 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000b5c wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b60 wid: 0 rd: -1 rs1: 14 rs2: 15 is_lw: 0 is_sw: 1 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 229 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b5c wid: 0 rd: 15 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b60 wid: 0 rd: -1 rs1: 14 rs2: 15 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 230 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b60 wid: 0 rd: -1 rs1: 14 rs2: 15 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b64 help: in PC: 80000b64 CUrrent CODE: fa5ff06f DEBUG ../core.cpp:703: Fetched at 0x80000b64 DEBUG ../core.cpp:704: 0x80000b64: jal; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000b08 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 80001008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b64 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 231 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b60 wid: 0 rd: -1 rs1: 14 rs2: 15 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b64 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 232 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000b60 wid: 0 rd: -1 rs1: 14 rs2: 15 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b64 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 233 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000b64 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 234 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b64 wid: 0 rd: 0 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 235 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 236 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b08 help: in PC: 80000b08 CUrrent CODE: 47a703 DEBUG ../core.cpp:703: Fetched at 0x80000b08 DEBUG ../core.cpp:704: 0x80000b08: load; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b08 wid: 0 rd: 14 rs1: 15 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 237 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b08 wid: 0 rd: 14 rs1: 15 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b0c help: in PC: 80000b0c CUrrent CODE: 1f00813 DEBUG ../core.cpp:703: Fetched at 0x80000b0c DEBUG ../core.cpp:704: 0x80000b0c: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 0000001f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b0c wid: 0 rd: 16 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 238 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b08 wid: 0 rd: 14 rs1: 15 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b0c wid: 0 rd: 16 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b10 help: in PC: 80000b10 CUrrent CODE: 6e84e63 DEBUG ../core.cpp:703: Fetched at 0x80000b10 DEBUG ../core.cpp:704: 0x80000b10: branch; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 0000001f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b10 wid: 0 rd: -1 rs1: 16 rs2: 14 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 239 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000b08 wid: 0 rd: 14 rs1: 15 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b0c wid: 0 rd: 16 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b10 wid: 0 rd: -1 rs1: 16 rs2: 14 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 240 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b08 wid: 0 rd: 14 rs1: 15 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000b0c wid: 0 rd: 16 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b10 wid: 0 rd: -1 rs1: 16 rs2: 14 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 241 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b0c wid: 0 rd: 16 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b10 wid: 0 rd: -1 rs1: 16 rs2: 14 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 242 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b10 wid: 0 rd: -1 rs1: 16 rs2: 14 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 243 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b10 wid: 0 rd: -1 rs1: 16 rs2: 14 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 244 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000b10 wid: 0 rd: -1 rs1: 16 rs2: 14 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 245 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b10 wid: 0 rd: -1 rs1: 16 rs2: 14 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 246 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 247 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b14 help: in PC: 80000b14 CUrrent CODE: 271813 DEBUG ../core.cpp:703: Fetched at 0x80000b14 DEBUG ../core.cpp:704: 0x80000b14: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b14 wid: 0 rd: 16 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 248 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b14 wid: 0 rd: 16 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b18 help: in PC: 80000b18 CUrrent CODE: 2050663 DEBUG ../core.cpp:703: Fetched at 0x80000b18 DEBUG ../core.cpp:704: 0x80000b18: branch; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000b44 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b18 wid: 0 rd: -1 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 249 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b14 wid: 0 rd: 16 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b18 wid: 0 rd: -1 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 250 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000b14 wid: 0 rd: 16 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b18 wid: 0 rd: -1 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 251 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b14 wid: 0 rd: 16 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000b18 wid: 0 rd: -1 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 252 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b18 wid: 0 rd: -1 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 253 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 254 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b44 help: in PC: 80000b44 CUrrent CODE: 170713 DEBUG ../core.cpp:703: Fetched at 0x80000b44 DEBUG ../core.cpp:704: 0x80000b44: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b44 wid: 0 rd: 14 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 255 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b44 wid: 0 rd: 14 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 256 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b44 wid: 0 rd: 14 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 257 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b44 wid: 0 rd: 14 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 258 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b44 wid: 0 rd: 14 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b48 help: in PC: 80000b48 CUrrent CODE: e7a223 DEBUG ../core.cpp:703: Fetched at 0x80000b48 DEBUG ../core.cpp:704: 0x80000b48: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 80001154 + 4 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b48 wid: 0 rd: -1 rs1: 15 rs2: 14 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 259 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b44 wid: 0 rd: 14 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b48 wid: 0 rd: -1 rs1: 15 rs2: 14 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b4c help: in PC: 80000b4c CUrrent CODE: 10787b3 DEBUG ../core.cpp:703: Fetched at 0x80000b4c DEBUG ../core.cpp:704: 0x80000b4c: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b4c wid: 0 rd: 15 rs1: 15 rs2: 16 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 260 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000b44 wid: 0 rd: 14 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b48 wid: 0 rd: -1 rs1: 15 rs2: 14 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b4c wid: 0 rd: 15 rs1: 15 rs2: 16 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b50 help: in PC: 80000b50 CUrrent CODE: b7a423 DEBUG ../core.cpp:703: Fetched at 0x80000b50 DEBUG ../core.cpp:704: 0x80000b50: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 80001154 + 8 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b50 wid: 0 rd: -1 rs1: 15 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 261 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b44 wid: 0 rd: 14 rs1: 14 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b48 wid: 0 rd: -1 rs1: 15 rs2: 14 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 1 PC: 80000b4c wid: 0 rd: 15 rs1: 15 rs2: 16 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b50 wid: 0 rd: -1 rs1: 15 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 262 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000b48 wid: 0 rd: -1 rs1: 15 rs2: 14 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b4c wid: 0 rd: 15 rs1: 15 rs2: 16 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b50 wid: 0 rd: -1 rs1: 15 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b54 help: in PC: 80000b54 CUrrent CODE: 513 DEBUG ../core.cpp:703: Fetched at 0x80000b54 DEBUG ../core.cpp:704: 0x80000b54: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b54 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 263 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000b4c wid: 0 rd: 15 rs1: 15 rs2: 16 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b50 wid: 0 rd: -1 rs1: 15 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b54 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000b58 help: in PC: 80000b58 CUrrent CODE: 8067 DEBUG ../core.cpp:703: Fetched at 0x80000b58 DEBUG ../core.cpp:704: 0x80000b58: jalr; DEBUG ../instruction.cpp:350: Begin instruction execute. JALR_INST DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 8000003c DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b58 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 264 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b4c wid: 0 rd: 15 rs1: 15 rs2: 16 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b50 wid: 0 rd: -1 rs1: 15 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 1 PC: 80000b54 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000b58 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 265 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000b50 wid: 0 rd: -1 rs1: 15 rs2: 11 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b54 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000b58 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 266 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000b54 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000b58 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 267 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b54 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000b58 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 268 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000b58 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 269 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 270 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x8000003c help: in PC: 8000003c CUrrent CODE: 149000ef DEBUG ../core.cpp:703: Fetched at 0x8000003c DEBUG ../core.cpp:704: 0x8000003c: jal; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000984 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 8000003c wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 271 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000003c wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 272 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000003c wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 273 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000003c wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 274 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000003c wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 275 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 276 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000984 help: in PC: 80000984 CUrrent CODE: ff010113 DEBUG ../core.cpp:703: Fetched at 0x80000984 DEBUG ../core.cpp:704: 0x80000984: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000984 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 277 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000984 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 278 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000984 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 279 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000984 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 280 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000984 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000988 help: in PC: 80000988 CUrrent CODE: 812423 DEBUG ../core.cpp:703: Fetched at 0x80000988 DEBUG ../core.cpp:704: 0x80000988: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 6fffeff0 + 8 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000988 wid: 0 rd: -1 rs1: 2 rs2: 8 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 281 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000984 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000988 wid: 0 rd: -1 rs1: 2 rs2: 8 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x8000098c help: in PC: 8000098c CUrrent CODE: 1212023 DEBUG ../core.cpp:703: Fetched at 0x8000098c DEBUG ../core.cpp:704: 0x8000098c: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 6fffeff0 + 0 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 8000098c wid: 0 rd: -1 rs1: 2 rs2: 18 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 282 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000984 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000988 wid: 0 rd: -1 rs1: 2 rs2: 8 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000098c wid: 0 rd: -1 rs1: 2 rs2: 18 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000990 help: in PC: 80000990 CUrrent CODE: 80001437 DEBUG ../core.cpp:703: Fetched at 0x80000990 DEBUG ../core.cpp:704: 0x80000990: lui; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000990 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 283 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000984 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000988 wid: 0 rd: -1 rs1: 2 rs2: 8 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 1 PC: 8000098c wid: 0 rd: -1 rs1: 2 rs2: 18 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000990 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 284 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000988 wid: 0 rd: -1 rs1: 2 rs2: 8 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 2 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000098c wid: 0 rd: -1 rs1: 2 rs2: 18 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000990 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 285 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 8000098c wid: 0 rd: -1 rs1: 2 rs2: 18 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000990 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 286 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000990 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000994 help: in PC: 80000994 CUrrent CODE: 80001937 DEBUG ../core.cpp:703: Fetched at 0x80000994 DEBUG ../core.cpp:704: 0x80000994: lui; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000994 wid: 0 rd: 18 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 287 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000990 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000994 wid: 0 rd: 18 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000998 help: in PC: 80000998 CUrrent CODE: 40793 DEBUG ../core.cpp:703: Fetched at 0x80000998 DEBUG ../core.cpp:704: 0x80000998: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000998 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 288 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000990 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000994 wid: 0 rd: 18 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000998 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x8000099c help: in PC: 8000099c CUrrent CODE: 90913 DEBUG ../core.cpp:703: Fetched at 0x8000099c DEBUG ../core.cpp:704: 0x8000099c: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 8000099c wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 289 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000990 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000994 wid: 0 rd: 18 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000998 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 8000099c wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009a0 help: in PC: 800009a0 CUrrent CODE: 40f90933 DEBUG ../core.cpp:703: Fetched at 0x800009a0 DEBUG ../core.cpp:704: 0x800009a0: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009a0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 290 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000994 wid: 0 rd: 18 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000998 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 8000099c wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009a0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 291 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000998 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 8000099c wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009a0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 292 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 8000099c wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009a0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 293 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009a0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009a4 help: in PC: 800009a4 CUrrent CODE: 112623 DEBUG ../core.cpp:703: Fetched at 0x800009a4 DEBUG ../core.cpp:704: 0x800009a4: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 6fffeff0 + c DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009a4 wid: 0 rd: -1 rs1: 2 rs2: 1 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 294 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009a0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009a4 wid: 0 rd: -1 rs1: 2 rs2: 1 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009a8 help: in PC: 800009a8 CUrrent CODE: 912223 DEBUG ../core.cpp:703: Fetched at 0x800009a8 DEBUG ../core.cpp:704: 0x800009a8: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 6fffeff0 + 4 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009a8 wid: 0 rd: -1 rs1: 2 rs2: 9 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 295 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009a0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009a4 wid: 0 rd: -1 rs1: 2 rs2: 1 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009a8 wid: 0 rd: -1 rs1: 2 rs2: 9 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009ac help: in PC: 800009ac CUrrent CODE: 40295913 DEBUG ../core.cpp:703: Fetched at 0x800009ac DEBUG ../core.cpp:704: 0x800009ac: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009ac wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 296 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009a0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 800009a4 wid: 0 rd: -1 rs1: 2 rs2: 1 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009a8 wid: 0 rd: -1 rs1: 2 rs2: 9 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009ac wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009b0 help: in PC: 800009b0 CUrrent CODE: 2090063 DEBUG ../core.cpp:703: Fetched at 0x800009b0 DEBUG ../core.cpp:704: 0x800009b0: branch; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 800009d0 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009b0 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 297 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 800009a8 wid: 0 rd: -1 rs1: 2 rs2: 9 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009ac wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009b0 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 298 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009ac wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009b0 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 299 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009ac wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009b0 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 300 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009b0 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 301 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009b0 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 302 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009b0 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 303 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009b0 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 304 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 305 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009d0 help: in PC: 800009d0 CUrrent CODE: 80001437 DEBUG ../core.cpp:703: Fetched at 0x800009d0 DEBUG ../core.cpp:704: 0x800009d0: lui; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009d0 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 306 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009d0 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 307 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009d0 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 308 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009d0 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 309 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009d0 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009d4 help: in PC: 800009d4 CUrrent CODE: 80001937 DEBUG ../core.cpp:703: Fetched at 0x800009d4 DEBUG ../core.cpp:704: 0x800009d4: lui; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009d4 wid: 0 rd: 18 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 310 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009d0 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009d4 wid: 0 rd: 18 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009d8 help: in PC: 800009d8 CUrrent CODE: 40793 DEBUG ../core.cpp:703: Fetched at 0x800009d8 DEBUG ../core.cpp:704: 0x800009d8: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009d8 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 311 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009d0 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009d4 wid: 0 rd: 18 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009d8 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009dc help: in PC: 800009dc CUrrent CODE: 490913 DEBUG ../core.cpp:703: Fetched at 0x800009dc DEBUG ../core.cpp:704: 0x800009dc: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009dc wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 312 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009d0 wid: 0 rd: 8 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009d4 wid: 0 rd: 18 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009d8 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009dc wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009e0 help: in PC: 800009e0 CUrrent CODE: 40f90933 DEBUG ../core.cpp:703: Fetched at 0x800009e0 DEBUG ../core.cpp:704: 0x800009e0: r_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009e0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 313 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009d4 wid: 0 rd: 18 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009d8 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009dc wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009e0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 314 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009d8 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009dc wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009e0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 315 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009dc wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009e0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 316 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009e0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009e4 help: in PC: 800009e4 CUrrent CODE: 40295913 DEBUG ../core.cpp:703: Fetched at 0x800009e4 DEBUG ../core.cpp:704: 0x800009e4: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009e4 wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 317 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009e0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009e4 wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009e8 help: in PC: 800009e8 CUrrent CODE: 2090063 DEBUG ../core.cpp:703: Fetched at 0x800009e8 DEBUG ../core.cpp:704: 0x800009e8: branch; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009e8 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 318 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009e0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009e4 wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009e8 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 319 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009e0 wid: 0 rd: 18 rs1: 18 rs2: 15 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009e4 wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 1 PC: 800009e8 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 320 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009e4 wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009e8 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 321 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009e4 wid: 0 rd: 18 rs1: 18 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009e8 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 322 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009e8 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 323 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009e8 wid: 0 rd: -1 rs1: 18 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 324 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 325 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009ec help: in PC: 800009ec CUrrent CODE: 40413 DEBUG ../core.cpp:703: Fetched at 0x800009ec DEBUG ../core.cpp:704: 0x800009ec: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009ec wid: 0 rd: 8 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 326 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009ec wid: 0 rd: 8 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009f0 help: in PC: 800009f0 CUrrent CODE: 493 DEBUG ../core.cpp:703: Fetched at 0x800009f0 DEBUG ../core.cpp:704: 0x800009f0: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009f0 wid: 0 rd: 9 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 327 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009ec wid: 0 rd: 8 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009f0 wid: 0 rd: 9 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 328 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009ec wid: 0 rd: 8 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009f0 wid: 0 rd: 9 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 329 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009ec wid: 0 rd: 8 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800009f0 wid: 0 rd: 9 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 330 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009f0 wid: 0 rd: 9 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009f4 help: in PC: 800009f4 CUrrent CODE: 42783 DEBUG ../core.cpp:703: Fetched at 0x800009f4 DEBUG ../core.cpp:704: 0x800009f4: load; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80000050 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009f4 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 331 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009f0 wid: 0 rd: 9 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009f4 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009f8 help: in PC: 800009f8 CUrrent CODE: 148493 DEBUG ../core.cpp:703: Fetched at 0x800009f8 DEBUG ../core.cpp:704: 0x800009f8: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80000050 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009f8 wid: 0 rd: 9 rs1: 9 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 332 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009f0 wid: 0 rd: 9 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009f4 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009f8 wid: 0 rd: 9 rs1: 9 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800009fc help: in PC: 800009fc CUrrent CODE: 440413 DEBUG ../core.cpp:703: Fetched at 0x800009fc DEBUG ../core.cpp:704: 0x800009fc: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80000050 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800009fc wid: 0 rd: 8 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 333 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009f0 wid: 0 rd: 9 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 800009f4 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 2 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009f8 wid: 0 rd: 9 rs1: 9 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800009fc wid: 0 rd: 8 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a00 help: in PC: 80000a00 CUrrent CODE: 780e7 DEBUG ../core.cpp:703: Fetched at 0x80000a00 DEBUG ../core.cpp:704: 0x80000a00: jalr; DEBUG ../instruction.cpp:350: Begin instruction execute. JALR_INST DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000050 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000a04 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 80000050 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a00 wid: 0 rd: 1 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 334 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 800009f4 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 1 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009f8 wid: 0 rd: 9 rs1: 9 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800009fc wid: 0 rd: 8 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a00 wid: 0 rd: 1 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 335 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009f8 wid: 0 rd: 9 rs1: 9 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 800009f4 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800009fc wid: 0 rd: 8 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a00 wid: 0 rd: 1 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 336 Stalled Warps: 1 0 0 0 0 0 0 0 $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used ********************************** Writeback ********************************* valid: 1 PC: 800009fc wid: 0 rd: 8 rs1: 8 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 800009f4 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a00 wid: 0 rd: 1 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 337 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800009f4 wid: 0 rd: 15 rs1: 8 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a00 wid: 0 rd: 1 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 338 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a00 wid: 0 rd: 1 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 339 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000a00 wid: 0 rd: 1 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 340 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a00 wid: 0 rd: 1 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 341 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 342 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000050 help: in PC: 80000050 CUrrent CODE: 7b7 DEBUG ../core.cpp:703: Fetched at 0x80000050 DEBUG ../core.cpp:704: 0x80000050: lui; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000a04 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000050 wid: 0 rd: 15 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 343 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000050 wid: 0 rd: 15 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 344 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000050 wid: 0 rd: 15 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 345 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000050 wid: 0 rd: 15 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 346 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000050 wid: 0 rd: 15 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000054 help: in PC: 80000054 CUrrent CODE: 78793 DEBUG ../core.cpp:703: Fetched at 0x80000054 DEBUG ../core.cpp:704: 0x80000054: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000a04 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000054 wid: 0 rd: 15 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 347 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000050 wid: 0 rd: 15 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000054 wid: 0 rd: 15 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000058 help: in PC: 80000058 CUrrent CODE: 78863 DEBUG ../core.cpp:703: Fetched at 0x80000058 DEBUG ../core.cpp:704: 0x80000058: branch; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000068 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000a04 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000058 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 348 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000050 wid: 0 rd: 15 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000054 wid: 0 rd: 15 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000058 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 349 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000050 wid: 0 rd: 15 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000054 wid: 0 rd: 15 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 1 PC: 80000058 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 350 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000054 wid: 0 rd: 15 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000058 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 351 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000054 wid: 0 rd: 15 rs1: 15 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000058 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 352 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000058 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 353 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000058 wid: 0 rd: -1 rs1: 15 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 354 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 355 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000068 help: in PC: 80000068 CUrrent CODE: 8067 DEBUG ../core.cpp:703: Fetched at 0x80000068 DEBUG ../core.cpp:704: 0x80000068: jalr; DEBUG ../instruction.cpp:350: Begin instruction execute. JALR_INST DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000a04 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000a04 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000068 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 356 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000068 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 357 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000068 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 358 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000068 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 359 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000068 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 360 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 361 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a04 help: in PC: 80000a04 CUrrent CODE: fe9918e3 DEBUG ../core.cpp:703: Fetched at 0x80000a04 DEBUG ../core.cpp:704: 0x80000a04: branch; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000a04 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a04 wid: 0 rd: -1 rs1: 18 rs2: 9 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 362 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a04 wid: 0 rd: -1 rs1: 18 rs2: 9 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 363 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a04 wid: 0 rd: -1 rs1: 18 rs2: 9 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 364 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000a04 wid: 0 rd: -1 rs1: 18 rs2: 9 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 365 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a04 wid: 0 rd: -1 rs1: 18 rs2: 9 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 366 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 367 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a08 help: in PC: 80000a08 CUrrent CODE: c12083 DEBUG ../core.cpp:703: Fetched at 0x80000a08 DEBUG ../core.cpp:704: 0x80000a08: load; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a08 wid: 0 rd: 1 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 368 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a08 wid: 0 rd: 1 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a0c help: in PC: 80000a0c CUrrent CODE: 812403 DEBUG ../core.cpp:703: Fetched at 0x80000a0c DEBUG ../core.cpp:704: 0x80000a0c: load; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a0c wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 369 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a08 wid: 0 rd: 1 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a0c wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a10 help: in PC: 80000a10 CUrrent CODE: 412483 DEBUG ../core.cpp:703: Fetched at 0x80000a10 DEBUG ../core.cpp:704: 0x80000a10: load; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a10 wid: 0 rd: 9 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 370 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000a08 wid: 0 rd: 1 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a0c wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a10 wid: 0 rd: 9 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 371 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a08 wid: 0 rd: 1 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000a0c wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a10 wid: 0 rd: 9 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 372 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a0c wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a10 wid: 0 rd: 9 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 373 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a10 wid: 0 rd: 9 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a14 help: in PC: 80000a14 CUrrent CODE: 12903 DEBUG ../core.cpp:703: Fetched at 0x80000a14 DEBUG ../core.cpp:704: 0x80000a14: load; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a14 wid: 0 rd: 18 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 374 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a10 wid: 0 rd: 9 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a14 wid: 0 rd: 18 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a18 help: in PC: 80000a18 CUrrent CODE: 1010113 DEBUG ../core.cpp:703: Fetched at 0x80000a18 DEBUG ../core.cpp:704: 0x80000a18: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a18 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 375 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000a10 wid: 0 rd: 9 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a14 wid: 0 rd: 18 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a18 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000a1c help: in PC: 80000a1c CUrrent CODE: 8067 DEBUG ../core.cpp:703: Fetched at 0x80000a1c DEBUG ../core.cpp:704: 0x80000a1c: jalr; DEBUG ../instruction.cpp:350: Begin instruction execute. JALR_INST DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 80000040 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000a1c wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 376 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a10 wid: 0 rd: 9 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 80000a14 wid: 0 rd: 18 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a18 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000a1c wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 377 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a14 wid: 0 rd: 18 rs1: 2 rs2: -1 is_lw: 1 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000a18 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000a1c wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 378 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a18 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000a1c wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 379 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000a1c wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 380 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 381 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000040 help: in PC: 80000040 CUrrent CODE: 400513 DEBUG ../core.cpp:703: Fetched at 0x80000040 DEBUG ../core.cpp:704: 0x80000040: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000040 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 382 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000040 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 383 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000040 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 384 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 80000040 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 385 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000040 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x80000044 help: in PC: 80000044 CUrrent CODE: 5006b DEBUG ../core.cpp:703: Fetched at 0x80000044 DEBUG ../core.cpp:704: 0x80000044: gpgpu; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000044 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 386 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000040 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000044 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 387 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000040 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000044 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 388 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000040 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000044 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 389 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000044 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 390 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000044 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 391 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 392 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x80000048 help: in PC: 80000048 CUrrent CODE: 5d000ef DEBUG ../core.cpp:703: Fetched at 0x80000048 DEBUG ../core.cpp:704: 0x80000048: jal; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 800008a4 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000004c 8000004c 8000004c 8000004c 00000000 00000000 00000000 00000000 (0) %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 80000048 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 393 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 80000048 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 394 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 80000048 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 395 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 80000048 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 396 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 80000048 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 397 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 398 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x800008a4 help: in PC: 800008a4 CUrrent CODE: ff010113 DEBUG ../core.cpp:703: Fetched at 0x800008a4 DEBUG ../core.cpp:704: 0x800008a4: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000004c 8000004c 8000004c 8000004c 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008a4 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 399 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008a4 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 400 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008a4 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 401 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008a4 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 402 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008a4 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x800008a8 help: in PC: 800008a8 CUrrent CODE: 112623 DEBUG ../core.cpp:703: Fetched at 0x800008a8 DEBUG ../core.cpp:704: 0x800008a8: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 6fffeff0 + c STORE MEM ADDRESS: 6fffebf4 + c STORE MEM ADDRESS: 6fffe7f8 + c STORE MEM ADDRESS: 6fffe3fc + c DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000004c 8000004c 8000004c 8000004c 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008a8 wid: 0 rd: -1 rs1: 2 rs2: 1 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 9 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 403 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008a4 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008a8 wid: 0 rd: -1 rs1: 2 rs2: 1 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 9 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x800008ac help: in PC: 800008ac CUrrent CODE: 812423 DEBUG ../core.cpp:703: Fetched at 0x800008ac DEBUG ../core.cpp:704: 0x800008ac: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 6fffeff0 + 8 STORE MEM ADDRESS: 6fffebf4 + 8 STORE MEM ADDRESS: 6fffe7f8 + 8 STORE MEM ADDRESS: 6fffe3fc + 8 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000004c 8000004c 8000004c 8000004c 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008ac wid: 0 rd: -1 rs1: 2 rs2: 8 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 404 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800008a4 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008a8 wid: 0 rd: -1 rs1: 2 rs2: 1 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 9 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008ac wid: 0 rd: -1 rs1: 2 rs2: 8 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x800008b0 help: in PC: 800008b0 CUrrent CODE: 1010413 DEBUG ../core.cpp:703: Fetched at 0x800008b0 DEBUG ../core.cpp:704: 0x800008b0: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000004c 8000004c 8000004c 8000004c 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008b0 wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 405 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800008a4 wid: 0 rd: 2 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008a8 wid: 0 rd: -1 rs1: 2 rs2: 1 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 9 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 1 PC: 800008ac wid: 0 rd: -1 rs1: 2 rs2: 8 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008b0 wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 406 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 800008a8 wid: 0 rd: -1 rs1: 2 rs2: 1 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 8 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008ac wid: 0 rd: -1 rs1: 2 rs2: 8 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008b0 wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 407 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 800008ac wid: 0 rd: -1 rs1: 2 rs2: 8 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 2 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008b0 wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 408 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008b0 wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x800008b4 help: in PC: 800008b4 CUrrent CODE: 100513 DEBUG ../core.cpp:703: Fetched at 0x800008b4 DEBUG ../core.cpp:704: 0x800008b4: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 8000004c 8000004c 8000004c 8000004c 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 409 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008b0 wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x800008b8 help: in PC: 800008b8 CUrrent CODE: f41ff0ef DEBUG ../core.cpp:703: Fetched at 0x800008b8 DEBUG ../core.cpp:704: 0x800008b8: jal; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 800007f8 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008bc 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 1 1 1 0 0 0 0 DEBUG ../core.cpp:388: Now 4 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008b8 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 410 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800008b0 wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008b8 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 411 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800008b0 wid: 0 rd: 8 rs1: 2 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800008b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008b8 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 412 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800008b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800008b8 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 413 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800008b8 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 414 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 415 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[4] DEBUG ../core.cpp:683: in step pc=0x800007f8 help: in PC: 800007f8 CUrrent CODE: 5006b DEBUG ../core.cpp:703: Fetched at 0x800007f8 DEBUG ../core.cpp:704: 0x800007f8: gpgpu; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008bc 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 416 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 417 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 418 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 419 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 420 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 421 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 422 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 423 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 424 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800007fc help: in PC: 800007fc CUrrent CODE: 8067 DEBUG ../core.cpp:703: Fetched at 0x800007fc DEBUG ../core.cpp:704: 0x800007fc: jalr; DEBUG ../instruction.cpp:350: Begin instruction execute. JALR_INST DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 800008bc DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008bc 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800007fc wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 425 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800007fc wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 426 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800007fc wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 427 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800007fc wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 428 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800007fc wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 429 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 430 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800008bc help: in PC: 800008bc CUrrent CODE: ff8ff0ef DEBUG ../core.cpp:703: Fetched at 0x800008bc DEBUG ../core.cpp:704: 0x800008bc: jal; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 800000b4 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008bc wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 431 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008bc wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 432 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008bc wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 433 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800008bc wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 434 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800008bc wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 435 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 436 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000b4 help: in PC: 800000b4 CUrrent CODE: 200513 DEBUG ../core.cpp:703: Fetched at 0x800000b4 DEBUG ../core.cpp:704: 0x800000b4: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000002 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 437 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 438 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 439 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 440 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000b8 help: in PC: 800000b8 CUrrent CODE: 8572d7 Entered here: instr type = vector87 Entered here: instr type = vector Entered here: imm instrDEBUG ../enc.cpp:247: immed8 DEBUG ../enc.cpp:250: lmul 0 DEBUG ../enc.cpp:252: ediv 0 DEBUG ../enc.cpp:254: sew 2 DEBUG ../core.cpp:703: Fetched at 0x800000b8 DEBUG ../core.cpp:704: 0x800000b8: vsetvl; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:1091: VSET_ARITH DEBUG ../instruction.cpp:2004: lmul:1 sew:32 ediv: 1 DEBUG ../instruction.cpp:2014: VL:2 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000002 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000b8 wid: 0 rd: 5 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 441 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000b8 wid: 0 rd: 5 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000bc help: in PC: 800000bc CUrrent CODE: a00513 DEBUG ../core.cpp:703: Fetched at 0x800000bc DEBUG ../core.cpp:704: 0x800000bc: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000bc wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 442 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000b8 wid: 0 rd: 5 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000bc wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000c0 help: in PC: 800000c0 CUrrent CODE: a5a023 DEBUG ../core.cpp:703: Fetched at 0x800000c0 DEBUG ../core.cpp:704: 0x800000c0: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 80000924 + 0 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000c0 wid: 0 rd: -1 rs1: 11 rs2: 10 is_lw: 0 is_sw: 1 fetch_stall_cycles: 3 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 443 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000b4 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000b8 wid: 0 rd: 5 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 1 PC: 800000bc wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000c0 wid: 0 rd: -1 rs1: 11 rs2: 10 is_lw: 0 is_sw: 1 fetch_stall_cycles: 2 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 444 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000b8 wid: 0 rd: 5 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000bc wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000c0 wid: 0 rd: -1 rs1: 11 rs2: 10 is_lw: 0 is_sw: 1 fetch_stall_cycles: 1 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 445 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000b8 wid: 0 rd: 5 rs1: 10 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000bc wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000c0 wid: 0 rd: -1 rs1: 11 rs2: 10 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 446 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000bc wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000c0 wid: 0 rd: -1 rs1: 11 rs2: 10 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000c4 help: in PC: 800000c4 CUrrent CODE: 2a5a023 DEBUG ../core.cpp:703: Fetched at 0x800000c4 DEBUG ../core.cpp:704: 0x800000c4: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 80000924 + 20 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000c4 wid: 0 rd: -1 rs1: 11 rs2: 10 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 447 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000c0 wid: 0 rd: -1 rs1: 11 rs2: 10 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000c4 wid: 0 rd: -1 rs1: 11 rs2: 10 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000c8 help: in PC: 800000c8 CUrrent CODE: 1205e087 Entered here: instr type = vector7 DEBUG ../enc.cpp:275: vector load instr DEBUG ../core.cpp:703: Fetched at 0x800000c8 DEBUG ../core.cpp:704: 0x800000c8: vl; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2035: Executing vector load DEBUG ../instruction.cpp:2037: lmul: 1 VLEN:96sew: 32 DEBUG ../instruction.cpp:2038: src: 11 2147485988 DEBUG ../instruction.cpp:2039: dest1 DEBUG ../instruction.cpp:2040: width6 DEBUG ../instruction.cpp:2048: Data read 10 DEBUG ../instruction.cpp:2048: Data read 10 DEBUG ../instruction.cpp:2060: Vector Register state after addition: reg[0][0] = 0 reg[0][1] = 0 reg[0][2] = 0 reg[1][0] = 10 reg[1][1] = 10 reg[1][2] = 0 reg[2][0] = 0 reg[2][1] = 0 reg[2][2] = 0 reg[3][0] = 0 reg[3][1] = 0 reg[3][2] = 0 reg[4][0] = 0 reg[4][1] = 0 reg[4][2] = 0 reg[5][0] = 0 reg[5][1] = 0 reg[5][2] = 0 reg[6][0] = 0 reg[6][1] = 0 reg[6][2] = 0 reg[7][0] = 0 reg[7][1] = 0 reg[7][2] = 0 reg[8][0] = 0 reg[8][1] = 0 reg[8][2] = 0 reg[9][0] = 0 reg[9][1] = 0 reg[9][2] = 0 reg[10][0] = 0 reg[10][1] = 0 reg[10][2] = 0 reg[11][0] = 0 reg[11][1] = 0 reg[11][2] = 0 reg[12][0] = 0 reg[12][1] = 0 reg[12][2] = 0 reg[13][0] = 0 reg[13][1] = 0 reg[13][2] = 0 reg[14][0] = 0 reg[14][1] = 0 reg[14][2] = 0 reg[15][0] = 0 reg[15][1] = 0 reg[15][2] = 0 reg[16][0] = 0 reg[16][1] = 0 reg[16][2] = 0 reg[17][0] = 0 reg[17][1] = 0 reg[17][2] = 0 reg[18][0] = 0 reg[18][1] = 0 reg[18][2] = 0 reg[19][0] = 0 reg[19][1] = 0 reg[19][2] = 0 reg[20][0] = 0 reg[20][1] = 0 reg[20][2] = 0 reg[21][0] = 0 reg[21][1] = 0 reg[21][2] = 0 reg[22][0] = 0 reg[22][1] = 0 reg[22][2] = 0 reg[23][0] = 0 reg[23][1] = 0 reg[23][2] = 0 reg[24][0] = 0 reg[24][1] = 0 reg[24][2] = 0 reg[25][0] = 0 reg[25][1] = 0 reg[25][2] = 0 reg[26][0] = 0 reg[26][1] = 0 reg[26][2] = 0 reg[27][0] = 0 reg[27][1] = 0 reg[27][2] = 0 reg[28][0] = 0 reg[28][1] = 0 reg[28][2] = 0 reg[29][0] = 0 reg[29][1] = 0 reg[29][2] = 0 reg[30][0] = 0 reg[30][1] = 0 reg[30][2] = 0 reg[31][0] = 0 reg[31][1] = 0 reg[31][2] = 0 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000c8 wid: 0 rd: 1 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 448 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 800000c0 wid: 0 rd: -1 rs1: 11 rs2: 10 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 2 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000c4 wid: 0 rd: -1 rs1: 11 rs2: 10 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000c8 wid: 0 rd: 1 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000cc help: in PC: 800000cc CUrrent CODE: 100613 DEBUG ../core.cpp:703: Fetched at 0x800000cc DEBUG ../core.cpp:704: 0x800000cc: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000001 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000cc wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 449 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 800000c4 wid: 0 rd: -1 rs1: 11 rs2: 10 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 2 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000c8 wid: 0 rd: 1 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000cc wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000d0 help: in PC: 800000d0 CUrrent CODE: c6a023 DEBUG ../core.cpp:703: Fetched at 0x800000d0 DEBUG ../core.cpp:704: 0x800000d0: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 0 + 0 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000001 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000d0 wid: 0 rd: -1 rs1: 13 rs2: 12 is_lw: 0 is_sw: 1 fetch_stall_cycles: 3 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 450 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000c8 wid: 0 rd: 1 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000cc wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000d0 wid: 0 rd: -1 rs1: 13 rs2: 12 is_lw: 0 is_sw: 1 fetch_stall_cycles: 2 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 451 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000c8 wid: 0 rd: 1 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000cc wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000d0 wid: 0 rd: -1 rs1: 13 rs2: 12 is_lw: 0 is_sw: 1 fetch_stall_cycles: 1 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 452 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000cc wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000d0 wid: 0 rd: -1 rs1: 13 rs2: 12 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 453 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000d0 wid: 0 rd: -1 rs1: 13 rs2: 12 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000d4 help: in PC: 800000d4 CUrrent CODE: 613 DEBUG ../core.cpp:703: Fetched at 0x800000d4 DEBUG ../core.cpp:704: 0x800000d4: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000d4 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 454 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000d0 wid: 0 rd: -1 rs1: 13 rs2: 12 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 3 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000d4 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000d8 help: in PC: 800000d8 CUrrent CODE: 2c6a023 DEBUG ../core.cpp:703: Fetched at 0x800000d8 DEBUG ../core.cpp:704: 0x800000d8: store; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 0 + 20 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000d8 wid: 0 rd: -1 rs1: 13 rs2: 12 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 455 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 800000d0 wid: 0 rd: -1 rs1: 13 rs2: 12 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 2 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000d4 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000d8 wid: 0 rd: -1 rs1: 13 rs2: 12 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000dc help: in PC: 800000dc CUrrent CODE: 1206e007 Entered here: instr type = vector7 DEBUG ../enc.cpp:275: vector load instr DEBUG ../core.cpp:703: Fetched at 0x800000dc DEBUG ../core.cpp:704: 0x800000dc: vl; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2035: Executing vector load DEBUG ../instruction.cpp:2037: lmul: 1 VLEN:96sew: 32 DEBUG ../instruction.cpp:2038: src: 13 0 DEBUG ../instruction.cpp:2039: dest0 DEBUG ../instruction.cpp:2040: width6 DEBUG ../instruction.cpp:2048: Data read 1 DEBUG ../instruction.cpp:2048: Data read 0 DEBUG ../instruction.cpp:2060: Vector Register state after addition: reg[0][0] = 1 reg[0][1] = 0 reg[0][2] = 0 reg[1][0] = 10 reg[1][1] = 10 reg[1][2] = 0 reg[2][0] = 0 reg[2][1] = 0 reg[2][2] = 0 reg[3][0] = 0 reg[3][1] = 0 reg[3][2] = 0 reg[4][0] = 0 reg[4][1] = 0 reg[4][2] = 0 reg[5][0] = 0 reg[5][1] = 0 reg[5][2] = 0 reg[6][0] = 0 reg[6][1] = 0 reg[6][2] = 0 reg[7][0] = 0 reg[7][1] = 0 reg[7][2] = 0 reg[8][0] = 0 reg[8][1] = 0 reg[8][2] = 0 reg[9][0] = 0 reg[9][1] = 0 reg[9][2] = 0 reg[10][0] = 0 reg[10][1] = 0 reg[10][2] = 0 reg[11][0] = 0 reg[11][1] = 0 reg[11][2] = 0 reg[12][0] = 0 reg[12][1] = 0 reg[12][2] = 0 reg[13][0] = 0 reg[13][1] = 0 reg[13][2] = 0 reg[14][0] = 0 reg[14][1] = 0 reg[14][2] = 0 reg[15][0] = 0 reg[15][1] = 0 reg[15][2] = 0 reg[16][0] = 0 reg[16][1] = 0 reg[16][2] = 0 reg[17][0] = 0 reg[17][1] = 0 reg[17][2] = 0 reg[18][0] = 0 reg[18][1] = 0 reg[18][2] = 0 reg[19][0] = 0 reg[19][1] = 0 reg[19][2] = 0 reg[20][0] = 0 reg[20][1] = 0 reg[20][2] = 0 reg[21][0] = 0 reg[21][1] = 0 reg[21][2] = 0 reg[22][0] = 0 reg[22][1] = 0 reg[22][2] = 0 reg[23][0] = 0 reg[23][1] = 0 reg[23][2] = 0 reg[24][0] = 0 reg[24][1] = 0 reg[24][2] = 0 reg[25][0] = 0 reg[25][1] = 0 reg[25][2] = 0 reg[26][0] = 0 reg[26][1] = 0 reg[26][2] = 0 reg[27][0] = 0 reg[27][1] = 0 reg[27][2] = 0 reg[28][0] = 0 reg[28][1] = 0 reg[28][2] = 0 reg[29][0] = 0 reg[29][1] = 0 reg[29][2] = 0 reg[30][0] = 0 reg[30][1] = 0 reg[30][2] = 0 reg[31][0] = 0 reg[31][1] = 0 reg[31][2] = 0 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000dc wid: 0 rd: 0 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 456 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000d4 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000d8 wid: 0 rd: -1 rs1: 13 rs2: 12 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000dc wid: 0 rd: 0 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000e0 help: in PC: 800000e0 CUrrent CODE: 6a01a057 Entered here: instr type = vector87 Entered here: instr type = vector DEBUG ../core.cpp:703: Fetched at 0x800000e0 DEBUG ../core.cpp:704: 0x800000e0: vsetvl; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:1091: VSET_ARITH DEBUG ../instruction.cpp:1632: vmor Comparing 0 + 1 = 1 Comparing 0 + 0 = 0 VLMAX: 3 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000e0 wid: 0 rd: 0 rs1: 3 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 457 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000d4 wid: 0 rd: 12 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000d8 wid: 0 rd: -1 rs1: 13 rs2: 12 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 1 ********************************** Decode ********************************* valid: 1 PC: 800000dc wid: 0 rd: 0 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000e0 wid: 0 rd: 0 rs1: 3 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 458 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 1 PC: 800000d8 wid: 0 rd: -1 rs1: 13 rs2: 12 is_lw: 0 is_sw: 1 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000dc wid: 0 rd: 0 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000e0 wid: 0 rd: 0 rs1: 3 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 459 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000dc wid: 0 rd: 0 rs1: 13 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000e0 wid: 0 rd: 0 rs1: 3 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 460 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000e0 wid: 0 rd: 0 rs1: 3 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000e4 help: in PC: 800000e4 CUrrent CODE: 1080d7 Entered here: instr type = vector87 Entered here: instr type = vector DEBUG ../core.cpp:703: Fetched at 0x800000e4 DEBUG ../core.cpp:704: 0x800000e4: vsetvl; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:1091: VSET_ARITH DEBUG ../instruction.cpp:1101: Addition 1 1 Dest:1 Doing 32 bit vector addition Adding 10 + 10 = 20 DEBUG ../instruction.cpp:1163: Vector Register state after addition: reg[0][0] = 1 reg[0][1] = 0 reg[0][2] = 0 reg[1][0] = 20 reg[1][1] = 10 reg[1][2] = 0 reg[2][0] = 0 reg[2][1] = 0 reg[2][2] = 0 reg[3][0] = 0 reg[3][1] = 0 reg[3][2] = 0 reg[4][0] = 0 reg[4][1] = 0 reg[4][2] = 0 reg[5][0] = 0 reg[5][1] = 0 reg[5][2] = 0 reg[6][0] = 0 reg[6][1] = 0 reg[6][2] = 0 reg[7][0] = 0 reg[7][1] = 0 reg[7][2] = 0 reg[8][0] = 0 reg[8][1] = 0 reg[8][2] = 0 reg[9][0] = 0 reg[9][1] = 0 reg[9][2] = 0 reg[10][0] = 0 reg[10][1] = 0 reg[10][2] = 0 reg[11][0] = 0 reg[11][1] = 0 reg[11][2] = 0 reg[12][0] = 0 reg[12][1] = 0 reg[12][2] = 0 reg[13][0] = 0 reg[13][1] = 0 reg[13][2] = 0 reg[14][0] = 0 reg[14][1] = 0 reg[14][2] = 0 reg[15][0] = 0 reg[15][1] = 0 reg[15][2] = 0 reg[16][0] = 0 reg[16][1] = 0 reg[16][2] = 0 reg[17][0] = 0 reg[17][1] = 0 reg[17][2] = 0 reg[18][0] = 0 reg[18][1] = 0 reg[18][2] = 0 reg[19][0] = 0 reg[19][1] = 0 reg[19][2] = 0 reg[20][0] = 0 reg[20][1] = 0 reg[20][2] = 0 reg[21][0] = 0 reg[21][1] = 0 reg[21][2] = 0 reg[22][0] = 0 reg[22][1] = 0 reg[22][2] = 0 reg[23][0] = 0 reg[23][1] = 0 reg[23][2] = 0 reg[24][0] = 0 reg[24][1] = 0 reg[24][2] = 0 reg[25][0] = 0 reg[25][1] = 0 reg[25][2] = 0 reg[26][0] = 0 reg[26][1] = 0 reg[26][2] = 0 reg[27][0] = 0 reg[27][1] = 0 reg[27][2] = 0 reg[28][0] = 0 reg[28][1] = 0 reg[28][2] = 0 reg[29][0] = 0 reg[29][1] = 0 reg[29][2] = 0 reg[30][0] = 0 reg[30][1] = 0 reg[30][2] = 0 reg[31][0] = 0 reg[31][1] = 0 reg[31][2] = 0 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000e4 wid: 0 rd: 1 rs1: 1 rs2: 1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 461 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000e0 wid: 0 rd: 0 rs1: 3 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000e4 wid: 0 rd: 1 rs1: 1 rs2: 1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000e8 help: in PC: 800000e8 CUrrent CODE: 205e0a7 Entered here: instr type = vector39 DEBUG ../core.cpp:703: Fetched at 0x800000e8 DEBUG ../core.cpp:704: 0x800000e8: vs; DEBUG ../instruction.cpp:350: Begin instruction execute. STORE MEM ADDRESS: 80000924 DEBUG ../instruction.cpp:2100: store: 2147485988 value:20 STORE MEM ADDRESS: 80000944 DEBUG ../instruction.cpp:2100: store: 2147486020 value:10 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000e8 wid: 0 rd: 1 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 462 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000e0 wid: 0 rd: 0 rs1: 3 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000e4 wid: 0 rd: 1 rs1: 1 rs2: 1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000e8 wid: 0 rd: 1 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000ec help: in PC: 800000ec CUrrent CODE: 1205e287 Entered here: instr type = vector7 DEBUG ../enc.cpp:275: vector load instr DEBUG ../core.cpp:703: Fetched at 0x800000ec DEBUG ../core.cpp:704: 0x800000ec: vl; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2035: Executing vector load DEBUG ../instruction.cpp:2037: lmul: 1 VLEN:96sew: 32 DEBUG ../instruction.cpp:2038: src: 11 2147485988 DEBUG ../instruction.cpp:2039: dest5 DEBUG ../instruction.cpp:2040: width6 DEBUG ../instruction.cpp:2048: Data read 20 DEBUG ../instruction.cpp:2048: Data read 10 DEBUG ../instruction.cpp:2060: Vector Register state after addition: reg[0][0] = 1 reg[0][1] = 0 reg[0][2] = 0 reg[1][0] = 20 reg[1][1] = 10 reg[1][2] = 0 reg[2][0] = 0 reg[2][1] = 0 reg[2][2] = 0 reg[3][0] = 0 reg[3][1] = 0 reg[3][2] = 0 reg[4][0] = 0 reg[4][1] = 0 reg[4][2] = 0 reg[5][0] = 20 reg[5][1] = 10 reg[5][2] = 0 reg[6][0] = 0 reg[6][1] = 0 reg[6][2] = 0 reg[7][0] = 0 reg[7][1] = 0 reg[7][2] = 0 reg[8][0] = 0 reg[8][1] = 0 reg[8][2] = 0 reg[9][0] = 0 reg[9][1] = 0 reg[9][2] = 0 reg[10][0] = 0 reg[10][1] = 0 reg[10][2] = 0 reg[11][0] = 0 reg[11][1] = 0 reg[11][2] = 0 reg[12][0] = 0 reg[12][1] = 0 reg[12][2] = 0 reg[13][0] = 0 reg[13][1] = 0 reg[13][2] = 0 reg[14][0] = 0 reg[14][1] = 0 reg[14][2] = 0 reg[15][0] = 0 reg[15][1] = 0 reg[15][2] = 0 reg[16][0] = 0 reg[16][1] = 0 reg[16][2] = 0 reg[17][0] = 0 reg[17][1] = 0 reg[17][2] = 0 reg[18][0] = 0 reg[18][1] = 0 reg[18][2] = 0 reg[19][0] = 0 reg[19][1] = 0 reg[19][2] = 0 reg[20][0] = 0 reg[20][1] = 0 reg[20][2] = 0 reg[21][0] = 0 reg[21][1] = 0 reg[21][2] = 0 reg[22][0] = 0 reg[22][1] = 0 reg[22][2] = 0 reg[23][0] = 0 reg[23][1] = 0 reg[23][2] = 0 reg[24][0] = 0 reg[24][1] = 0 reg[24][2] = 0 reg[25][0] = 0 reg[25][1] = 0 reg[25][2] = 0 reg[26][0] = 0 reg[26][1] = 0 reg[26][2] = 0 reg[27][0] = 0 reg[27][1] = 0 reg[27][2] = 0 reg[28][0] = 0 reg[28][1] = 0 reg[28][2] = 0 reg[29][0] = 0 reg[29][1] = 0 reg[29][2] = 0 reg[30][0] = 0 reg[30][1] = 0 reg[30][2] = 0 reg[31][0] = 0 reg[31][1] = 0 reg[31][2] = 0 DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000ec wid: 0 rd: 5 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 463 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000e4 wid: 0 rd: 1 rs1: 1 rs2: 1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000e8 wid: 0 rd: 1 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000ec wid: 0 rd: 5 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800000f0 help: in PC: 800000f0 CUrrent CODE: 8067 DEBUG ../core.cpp:703: Fetched at 0x800000f0 DEBUG ../core.cpp:704: 0x800000f0: jalr; DEBUG ../instruction.cpp:350: Begin instruction execute. JALR_INST DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 800008c0 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800000f0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 464 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000e4 wid: 0 rd: 1 rs1: 1 rs2: 1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000e8 wid: 0 rd: 1 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000ec wid: 0 rd: 5 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000f0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 465 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000e8 wid: 0 rd: 1 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000ec wid: 0 rd: 5 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000f0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 466 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000ec wid: 0 rd: 5 rs1: 11 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800000f0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 467 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800000f0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 468 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800000f0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 469 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800000f0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 470 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800000f0 wid: 0 rd: 0 rs1: 1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 471 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 472 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800008c0 help: in PC: 800008c0 CUrrent CODE: 513 DEBUG ../core.cpp:703: Fetched at 0x800008c0 DEBUG ../core.cpp:704: 0x800008c0: i_type; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008c0 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 3 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 473 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008c0 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 2 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 474 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008c0 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 1 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 475 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 1 PC: 800008c0 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 476 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008c0 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800008c4 help: in PC: 800008c4 CUrrent CODE: f35ff0ef DEBUG ../core.cpp:703: Fetched at 0x800008c4 DEBUG ../core.cpp:704: 0x800008c4: jal; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. Next PC: 800007f8 DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c8 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 1 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 1 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800008c4 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 477 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008c0 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800008c4 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 478 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800008c0 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800008c4 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 479 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800008c0 wid: 0 rd: 10 rs1: 0 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800008c4 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 480 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800008c4 wid: 0 rd: 1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 481 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 Warp ID 0 is running ------------------------------------------------------ CYCLE: 482 Stalled Warps: 0 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 DEBUG ../core.cpp:386: Core step stepping warp 0[1] DEBUG ../core.cpp:683: in step pc=0x800007f8 help: in PC: 800007f8 CUrrent CODE: 5006b DEBUG ../core.cpp:703: Fetched at 0x800007f8 DEBUG ../core.cpp:704: 0x800007f8: gpgpu; DEBUG ../instruction.cpp:350: Begin instruction execute. DEBUG ../instruction.cpp:2117: End instruction execute. DEBUG ../core.cpp:717: Register state: %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 1: 800008c8 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) DEBUG ../core.cpp:726: Thread mask: 0 0 0 0 0 0 0 0 DEBUG ../core.cpp:388: Now 0 active threads in 0 ********************************** Fetch ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 483 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 484 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 485 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 486 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 1 PC: 800007f8 wid: 0 rd: 0 rs1: 10 rs2: 0 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 1 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 1 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ------------------------------------------------------ CYCLE: 487 Stalled Warps: 1 0 0 0 0 0 0 0 ********************************** Writeback ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** LSU ********************************* valid: 0 PC: 0 wid: 0 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** execute_unit ********************************* valid: 0 PC: 0 wid: 2 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** scheduler ********************************* valid: 0 PC: 0 wid: 3 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Decode ********************************* valid: 0 PC: 0 wid: 4 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 ********************************** Fetch ********************************* valid: 0 PC: 0 wid: 5 rd: -1 rs1: -1 rs2: -1 is_lw: 0 is_sw: 0 fetch_stall_cycles: 0 mem_stall_cycles: 0 stall_warp: 0 wspawn: 0 stalled: 0 === Warp 0 === Steps : 0 Insts : 200 Loads : 0 Stores: 25 GRADE: FAILED 0 === Warp 1 === Steps : 0 Insts : 59 Loads : 0 Stores: 0 GRADE: FAILED 0 === Warp 2 === Steps : 0 Insts : 59 Loads : 0 Stores: 0 GRADE: FAILED 0 === Warp 3 === Steps : 0 Insts : 59 Loads : 0 Stores: 0 GRADE: FAILED 0 === Warp 4 === Steps : 0 Insts : 0 Loads : 0 Stores: 0 GRADE: FAILED 0 === Warp 5 === Steps : 0 Insts : 0 Loads : 0 Stores: 0 GRADE: FAILED 0 === Warp 6 === Steps : 0 Insts : 0 Loads : 0 Stores: 0 GRADE: FAILED 0 === Warp 7 === Steps : 0 Insts : 0 Loads : 0 Stores: 0 GRADE: FAILED 0