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Commit Graph
93 Commits
Author SHA1 Message Date
Blaise Tine 18c1dc2f0e fixed interface modports 2021-09-28 02:42:04 -07:00
Blaise Tine 9f34b2944c code refactoring for Vivado, sv2v, and yosys compatibility 2021-09-27 08:55:10 -04:00
Blaise Tine 0dfdf6cd4d Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-09-10 06:03:32 -04:00
Blaise Tine 18172fa611 AXI memory bus support 2021-09-10 01:36:01 -07:00
Blaise Tine 170c5d0c8a regression script update 2021-09-08 23:22:50 -04:00
Blaise Tine c06efbf480 minor update 2021-09-07 23:47:41 -07:00
Blaise Tine 53c8cddccf LKG build - minor update 2021-08-30 10:25:52 -07:00
Blaise Tine 90b50277d0 cache multi-porting fixes + optimization 2021-08-29 18:33:49 -07:00
Blaise Tine 12b8b4af24 minor updates 2021-08-28 15:21:40 -07:00
Blaise Tine cc259f60f6 minor update 2021-08-11 15:39:21 -07:00
Blaise Tine 90fa9eee7d minor update 2021-08-08 18:35:05 -07:00
Blaise Tine 91d4419fae new regression tests 2021-08-02 16:05:33 -07:00
Blaise Tine 6f0b5865e2 minor update 2021-07-25 02:35:34 -07:00
Blaise Tine c461b66b59 fix debug log gathering on failure 2021-07-24 10:20:05 -07:00
Blaise Tine 4ffbcb336f minor update 2021-07-22 14:20:02 -07:00
Blaise Tine 152d807301 parallelizing continious integration 2021-07-20 12:12:11 -07:00
Blaise Tine b0d8adc82b minor update 2021-07-16 06:44:28 -07:00
Blaise Tine 5c40422e4f dcache response bus optimization 2021-07-12 10:14:48 -07:00
Blaise Tine 93fee18d59 minor update 2021-07-01 02:59:44 -07:00
Blaise Tine 22e201c07c Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-06-29 10:12:36 -04:00
Blaise Tine cd387d2b5b documentation udpate 2021-06-29 07:04:27 -07:00
Blaise Tine 44c82f6e13 minor update 2021-06-29 08:13:22 -04:00
Blaise Tine d2f9c66840 minor update 2021-06-29 03:50:01 -07:00
Blaise Tine 79ebcc23d7 minor update 2021-06-29 03:45:57 -07:00
Blaise Tine e8c01e18d8 regression fixes 2021-06-29 04:32:32 -04:00
Blaise Tine 24bde18cb1 minor update 2021-06-28 23:21:25 -07:00
Blaise Tine 893bfd8e00 minor update 2021-06-28 06:05:25 -04:00
Blaise Tine 1ea738ed26 lkg build 2021-06-25 16:28:10 -07:00
Blaise Tine 2372067817 minor update 2021-06-22 09:30:36 -07:00
Blaise Tine e2743046a3 minor update 2021-06-14 01:07:47 -04:00
Blaise Tine 585b31cc6d tests layout fixes 2021-06-13 18:05:46 -07:00
Blaise Tine cadff791ab test layout fixes 2021-06-13 17:59:06 -07:00
Blaise Tine 03406c0a3f project tests refactoring 2021-06-13 17:42:04 -07:00
Blaise Tine 3071fb7a29 adding support for non-cacheable memory addressing 2021-06-06 13:35:55 -07:00
Blaise Tine df7d91d690 more testing 2021-05-26 15:29:39 -07:00
Blaise Tine 9b120e3bb4 minor update 2021-05-24 20:05:36 -07:00
Blaise Tine c81b1173b8 minor update 2021-05-24 18:20:46 -07:00
Blaise Tine 6107bf8247 minor fix 2021-05-04 11:05:07 -07:00
Blaise Tine 962e193563 blackbox update 2021-05-03 07:45:39 -07:00
Blaise Tine bac53e4ae1 minor update 2021-05-02 11:05:49 -07:00
Blaise Tine d504adb236 afu mem controller refactoring 2021-05-01 08:39:52 -07:00
Blaise Tine 95f057bc2e fpga build refactoring 2021-04-29 06:17:28 -07:00
Blaise Tine 8410c49f53 code refactoring: DRAM => MEM renaming 2021-04-26 00:58:48 -07:00
Blaise Tine 4cb98a25a7 enabling 128-bit dram bus 2021-04-24 00:31:27 -04:00
Blaise Tine 41413a51ba testing no-shared memory mode 2021-04-01 12:37:40 -07:00
Blaise Tine 79d1d309a5 llvm-riscv toolchain update 2021-03-09 08:11:59 -08:00
Blaise Tine 28d51e0cf9 minor update 2021-03-09 05:50:23 -08:00
Blaise Tine 3a266fc792 adding compiler tests to regression suite 2021-03-09 05:01:56 -08:00
Blaise Tine 848fc0c2df minor update 2021-03-09 00:07:05 -08:00
Blaise Tine 907e6868cd simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite 2021-03-08 23:58:33 -08:00