wu-arch/kernels
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6 Commits
Author SHA1 Message Date
Blaise Tine fe64c47f60 ccip write fix 2021-01-14 22:49:06 -08:00
Blaise Tine 29cd2f5dff fixed register file initialization to zero synthesis inference 2020-12-10 00:27:56 -08:00
Blaise Tine 43ae82e788 vlsim fix, verilator fst trace, use ram optimization 2020-10-25 16:40:50 -07:00
Blaise Tine 301cc45740 scope fixes 2020-10-14 09:19:26 -07:00
Blaise Tine 32da50816f scope refactoring: adding modules definitions to VCD trace 2020-10-12 23:26:02 -04:00
Blaise Tine 0fab1ddd92 adding support for verilator-driven AFU driver: vlsim 2020-09-08 13:05:26 -04:00