Blaise Tine
|
4bbd7bf408
|
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
|
2020-12-19 02:45:06 -08:00 |
|
Blaise Tine
|
d5fa82f5e4
|
cache req datapath optimizations
|
2020-12-08 02:58:08 -08:00 |
|
Blaise Tine
|
d68b32cd60
|
minor update
|
2020-12-06 22:40:27 -08:00 |
|
Blaise Tine
|
d0f2a3984d
|
adding input buffering to bus arbiters to reduce backpressure delay propagation
|
2020-12-05 17:31:29 -08:00 |
|
Blaise Tine
|
0a8f41964d
|
minor update
|
2020-12-03 08:47:03 -08:00 |
|
Blaise Tine
|
f3b1069ce8
|
adding stream arbiter
|
2020-12-03 06:40:23 -08:00 |
|
Blaise Tine
|
5758ef9ebf
|
generic_register reset network optimization
|
2020-11-29 18:41:36 -08:00 |
|
Blaise Tine
|
5d58bf3d11
|
fixed l3cache hang using memory arbiter in afu
|
2020-11-15 06:36:32 -08:00 |
|
Blaise Tine
|
725322807e
|
fixed DRAM response backpressure inside Cache
|
2020-11-10 05:24:57 -08:00 |
|
Blaise Tine
|
10505caae1
|
refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2
|
2020-11-08 01:31:46 -08:00 |
|
Blaise Tine
|
5be1d85648
|
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
|
2020-11-02 01:50:12 -08:00 |
|
Blaise Tine
|
6c12391338
|
pipeline refactoring - fmax >= 222 mhz
|
2020-08-14 21:50:14 -07:00 |
|
Blaise Tine
|
d3440de403
|
round robin arbiter + auto buffered queue + fixed dcache arbiter
|
2020-06-20 17:56:04 -04:00 |
|
Blaise Tine
|
9850a1f890
|
minor fixes
|
2020-06-15 00:20:56 -07:00 |
|
Blaise Tine
|
4fa540575c
|
fixed gpr_ram bug + io bus arbitration
|
2020-06-13 05:26:29 -07:00 |
|