felsabbagh3
|
f21eaec79f
|
Provisioned SM
|
2019-04-05 19:25:54 -04:00 |
|
felsabbagh3
|
166b9ae48d
|
Before Scratchpad
|
2019-04-05 17:56:05 -04:00 |
|
felsabbagh3
|
719ed25213
|
Cleanup
|
2019-03-31 16:30:37 -04:00 |
|
felsabbagh3
|
8c2ae97510
|
1 WARP 8 THREADS TESTED + FULLY WORKING
|
2019-03-31 05:21:00 -04:00 |
|
felsabbagh3
|
c83ef94d02
|
1 WARP 2 THREADS WORKING
|
2019-03-31 05:02:55 -04:00 |
|
felsabbagh3
|
4aac33b298
|
Using verilog For-loops + Passing all tests
|
2019-03-30 22:55:13 -04:00 |
|
felsabbagh3
|
52a839f84d
|
Using verilog For-loops + Passing all tests
|
2019-03-30 22:14:44 -04:00 |
|
felsabbagh3
|
a3a3b21de7
|
Using verilog For-loops + Passing all tests
|
2019-03-30 22:09:03 -04:00 |
|
felsabbagh3
|
99a0792a0c
|
Passing all tests with 2 threads
|
2019-03-30 03:54:20 -04:00 |
|
felsabbagh3
|
d02c3d25b7
|
sync
|
2019-03-27 13:52:13 -04:00 |
|
felsabbagh3
|
68f3ba84e5
|
Added HW threads - Infinite loop + fixed valid
|
2019-03-27 03:53:59 -04:00 |
|
felsabbagh3
|
9b42e79dcf
|
Added HW threads - Infinite loop
|
2019-03-27 03:44:14 -04:00 |
|
felsabbagh3
|
cc0fb0eece
|
better use of valid signal
|
2019-03-27 00:07:59 -04:00 |
|
felsabbagh3
|
7a528c5ef2
|
Packing data wires + ALU module
|
2019-03-26 19:17:11 -04:00 |
|
felsabbagh3
|
781c11c93f
|
Updated TODO
|
2019-03-22 04:21:21 -04:00 |
|