Blaise Tine
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859877a00d
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tex_unit partial update
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2021-03-20 08:40:57 -04:00 |
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Blaise Tine
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2cbc1c4161
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adding texture test to tex_demo
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2021-03-17 09:52:33 -04:00 |
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Blaise Tine
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676a13f30d
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tex refactoring and bug fixes
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2021-03-16 09:25:57 -04:00 |
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Krishna Yalamarthy
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72e06ef4fe
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Tex CSRs write support added
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2021-03-15 16:41:29 -04:00 |
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Blaise Tine
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3f5fd6d394
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using shiftreg-based skid buffers
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2021-02-28 02:20:09 -08:00 |
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Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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7560202f8b
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cache bank refactoring - removing unecessary core response fifo & restoring single port data access
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2021-02-21 21:47:46 -08:00 |
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Blaise Tine
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3c37db877a
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cache specialization for in-order DRAM reponses
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2021-02-13 20:23:29 -08:00 |
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Blaise Tine
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073964fdf7
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minor update
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2021-02-12 08:52:06 -08:00 |
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Blaise Tine
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665b97b810
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multi-ported cache support for streaming
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2021-02-08 16:13:32 -08:00 |
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Blaise Tine
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8775f63ec4
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lkg build rollout with 16cores optimization on arria10
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2021-01-24 16:49:22 -08:00 |
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Blaise Tine
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ce9ef840d6
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minor updates
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2021-01-18 04:22:40 -08:00 |
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Blaise Tine
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a046bd7a73
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cache pipeline optimization
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2021-01-17 17:19:52 -08:00 |
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Blaise Tine
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a69ba5ad7b
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cache flush support
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2021-01-17 05:50:29 -08:00 |
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Blaise Tine
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d4e7b28be8
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cache refactoring
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2021-01-17 00:18:56 -08:00 |
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Blaise Tine
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7c4823e65c
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fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
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2021-01-11 23:55:09 -08:00 |
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Blaise Tine
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e770824d47
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fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance
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2021-01-10 20:26:15 -08:00 |
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Blaise Tine
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8aea9cbe07
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minor update
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2021-01-06 21:39:15 -08:00 |
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Blaise Tine
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2b8435471a
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speeding up simulation using dedicated full dpi-based FPU core
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2021-01-06 18:44:06 -08:00 |
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Blaise Tine
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2d69ca5d67
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scratchpad optimization for stack access using custom bank offset aligned to stack size
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2021-01-02 16:00:00 -05:00 |
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Blaise Tine
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30d950ada2
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vx_spawn_warps redesign using opencl's style scheduler
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2021-01-01 14:13:48 -05:00 |
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Blaise Tine
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e4a00dd0d9
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fixed loader script stack setup
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2020-12-31 22:37:20 -05:00 |
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Blaise Tine
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d44144f72f
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FPU float<->int conversion optimization
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2020-12-29 15:37:45 -08:00 |
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Blaise Tine
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e83c4638a0
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FPU area optimization sharing fmadd hard block
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2020-12-27 17:31:10 -08:00 |
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Blaise Tine
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25df233005
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Adding Altera Stratix 10 support
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2020-12-27 10:44:57 -08:00 |
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Blaise Tine
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b2b8f190dd
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minor update
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2020-12-26 14:47:41 -08:00 |
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Blaise Tine
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33c431ed44
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multiplier unit optimization - using fifo for metadata, shift register optimization
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2020-12-26 11:23:21 -08:00 |
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Blaise Tine
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b459192dec
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critical path optimization - fpga fmax @4c = ~212 mhz
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2020-12-26 03:28:32 -08:00 |
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Blaise Tine
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703a861fe9
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added support for write-through cache, removed cache snooping support
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2020-12-23 23:51:02 -08:00 |
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Blaise Tine
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d956e268b9
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adding new performance counters (banks utilization and DRAM bus utilization)
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2020-12-22 12:33:45 -08:00 |
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Blaise Tine
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4b7d871d62
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allowing partial cache request submissions, io bus support broken
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2020-12-21 03:53:13 -08:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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d5438fd591
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merging perf counters
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2020-12-08 21:02:39 -08:00 |
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Xandy Liu
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1595ff08e2
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PERF pipeline stalls and cache
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2020-12-08 01:14:41 -05:00 |
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Blaise Tine
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268ad15098
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minor update
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2020-12-06 22:55:17 -08:00 |
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Blaise Tine
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d68b32cd60
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minor update
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2020-12-06 22:40:27 -08:00 |
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Blaise Tine
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1332970636
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refactoring cores clustering
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2020-12-06 14:42:12 -08:00 |
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Blaise Tine
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b2652527bb
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data/dram bus refactoring
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2020-12-06 03:37:22 -08:00 |
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Blaise Tine
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478d971389
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minor update
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2020-12-03 16:21:20 -08:00 |
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Blaise Tine
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0a8f41964d
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minor update
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2020-12-03 08:47:03 -08:00 |
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Blaise Tine
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b7a724410b
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update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache)
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2020-12-03 07:30:19 -08:00 |
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Blaise Tine
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f68af3bb84
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using mshr pending request size
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2020-12-01 00:54:25 -08:00 |
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Blaise Tine
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def6a35693
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shared memory optimization
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2020-11-29 15:04:31 -08:00 |
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Blaise Tine
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b85391389b
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rename MSRQ to MSHR
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2020-11-28 17:32:00 -05:00 |
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Blaise Tine
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00d7473268
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build warnings clean
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2020-11-28 14:59:13 -05:00 |
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Blaise Tine
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7ae770f4eb
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config update
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2020-11-21 12:27:42 -08:00 |
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Blaise Tine
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1795980a52
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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
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2020-11-21 09:47:56 -08:00 |
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Blaise Tine
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4d94d33e8d
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constant integration updates
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2020-11-15 09:12:48 -08:00 |
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Blaise Tine
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725322807e
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fixed DRAM response backpressure inside Cache
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2020-11-10 05:24:57 -08:00 |
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Blaise Tine
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10505caae1
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refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2
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2020-11-08 01:31:46 -08:00 |
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