Blaise Tine
|
a70562d386
|
set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18
|
2020-06-29 08:03:19 -07:00 |
|
Blaise Tine
|
27ea36440e
|
multiplier fixes
|
2020-06-28 14:39:18 -07:00 |
|
Blaise Tine
|
8302641510
|
fpga fixes
|
2020-06-27 14:03:20 -07:00 |
|
Blaise Tine
|
0a01385a2c
|
few updates
|
2020-06-23 09:28:24 -07:00 |
|
Blaise Tine
|
d6b0ef2b3c
|
scope refactoring + snoop invalidate
|
2020-06-12 00:04:31 -07:00 |
|
Blaise Tine
|
19f263c772
|
scope fixes
|
2020-06-09 20:49:36 -07:00 |
|
Blaise Tine
|
2ab90e9436
|
rtl refactoring
|
2020-05-05 13:31:50 -04:00 |
|
Blaise Tine
|
b7e892ee16
|
rtl refactoring
|
2020-05-05 10:46:48 -04:00 |
|
Blaise Tine
|
38f73af627
|
update
|
2020-04-21 17:50:42 -04:00 |
|