12 Commits

Include renames

Author	SHA1	Message	Date
Blaise Tine	fc70bb3a4a	databus optimization	2021-03-29 23:48:04 -07:00
Blaise Tine	3f5fd6d394	using shiftreg-based skid buffers	2021-02-28 02:20:09 -08:00
Blaise Tine	ab63ac9e5d	cache request interfaces update	2021-02-10 20:55:04 -08:00
Blaise Tine	8775f63ec4	lkg build rollout with 16cores optimization on arria10	2021-01-24 16:49:22 -08:00
Blaise Tine	8aea9cbe07	minor update	2021-01-06 21:39:15 -08:00
Blaise Tine	2058718f0f	minor updates	2021-01-06 07:18:14 -08:00
Blaise Tine	31ff70fd4e	minor updates	2021-01-05 15:03:41 -08:00
Blaise Tine	3fdc49971c	minor update	2020-12-24 09:22:44 -08:00
Blaise Tine	4b7d871d62	allowing partial cache request submissions, io bus support broken	2020-12-21 03:53:13 -08:00
Blaise Tine	4bbd7bf408	performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,	2020-12-19 02:45:06 -08:00
Blaise Tine	d5fa82f5e4	cache req datapath optimizations	2020-12-08 02:58:08 -08:00
Blaise Tine	b2652527bb	data/dram bus refactoring	2020-12-06 03:37:22 -08:00