Commit Graph
65 Commits
Author SHA1 Message Date
Blaise Tine 2372067817 minor update 2021-06-22 09:30:36 -07:00
Blaise Tine e2743046a3 minor update 2021-06-14 01:07:47 -04:00
Blaise Tine 585b31cc6d tests layout fixes 2021-06-13 18:05:46 -07:00
Blaise Tine cadff791ab test layout fixes 2021-06-13 17:59:06 -07:00
Blaise Tine 03406c0a3f project tests refactoring 2021-06-13 17:42:04 -07:00
Blaise Tine 3071fb7a29 adding support for non-cacheable memory addressing 2021-06-06 13:35:55 -07:00
Blaise Tine df7d91d690 more testing 2021-05-26 15:29:39 -07:00
Blaise Tine 9b120e3bb4 minor update 2021-05-24 20:05:36 -07:00
Blaise Tine c81b1173b8 minor update 2021-05-24 18:20:46 -07:00
Blaise Tine 6107bf8247 minor fix 2021-05-04 11:05:07 -07:00
Blaise Tine 962e193563 blackbox update 2021-05-03 07:45:39 -07:00
Blaise Tine bac53e4ae1 minor update 2021-05-02 11:05:49 -07:00
Blaise Tine d504adb236 afu mem controller refactoring 2021-05-01 08:39:52 -07:00
Blaise Tine 95f057bc2e fpga build refactoring 2021-04-29 06:17:28 -07:00
Blaise Tine 8410c49f53 code refactoring: DRAM => MEM renaming 2021-04-26 00:58:48 -07:00
Blaise Tine 4cb98a25a7 enabling 128-bit dram bus 2021-04-24 00:31:27 -04:00
Blaise Tine 41413a51ba testing no-shared memory mode 2021-04-01 12:37:40 -07:00
Blaise Tine 79d1d309a5 llvm-riscv toolchain update 2021-03-09 08:11:59 -08:00
Blaise Tine 28d51e0cf9 minor update 2021-03-09 05:50:23 -08:00
Blaise Tine 3a266fc792 adding compiler tests to regression suite 2021-03-09 05:01:56 -08:00
Blaise Tine 848fc0c2df minor update 2021-03-09 00:07:05 -08:00
Blaise Tine 907e6868cd simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite 2021-03-08 23:58:33 -08:00
Blaise Tine 41f09ffb55 minor update - allow independent driver cleanup 2021-02-28 18:19:26 -08:00
Blaise Tine 700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
Blaise Tine 6c1dc96626 simX refactoring + removed oldRTL + CSR updates 2021-02-06 12:52:54 -08:00
Blaise Tine 6a6711b735 minor update 2021-02-04 09:11:46 -08:00
Blaise Tine 7c4823e65c fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests 2021-01-11 23:55:09 -08:00
Blaise Tine 50cfc48c0a minor fix 2021-01-11 02:59:59 -08:00
Blaise Tine b2cfde5d6d enabling shared memory back 2020-12-31 19:19:14 -08:00
Blaise Tine 703a861fe9 added support for write-through cache, removed cache snooping support 2020-12-23 23:51:02 -08:00
Blaise Tine 4bbd7bf408 performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies, 2020-12-19 02:45:06 -08:00
Blaise Tine e0905f8352 minor update 2020-12-09 05:34:27 -08:00
Blaise Tine 707ba3760f minor update 2020-12-08 21:37:53 -08:00
Blaise Tine d5438fd591 merging perf counters 2020-12-08 21:02:39 -08:00
Blaise Tine d68b32cd60 minor update 2020-12-06 22:40:27 -08:00
Blaise Tine 1332970636 refactoring cores clustering 2020-12-06 14:42:12 -08:00
Blaise Tine f4ed1e97f7 minor update 2020-11-23 12:08:31 -08:00
Blaise Tine 2d4fef6dd6 fixed fp_noncomp bug, ci toolchain script update, increased DRAM latency to 100 cycles 2020-11-23 11:59:40 -08:00
Blaise Tine e281d32138 travis timeout workaround 2020-11-22 19:07:46 -08:00
Blaise Tine 23cf72d7f4 travis timeout workaround 2020-11-22 14:28:46 -08:00
Blaise Tine f9e1e11dc5 travis timeout workaround 2020-11-22 12:41:58 -08:00
Blaise Tine 20f22c7446 scope minor fix 2020-11-22 11:51:46 -08:00
Blaise Tine 93fb036c4f blackbox.sh update 2020-11-21 16:01:31 -08:00
Blaise Tine 1795980a52 L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization 2020-11-21 09:47:56 -08:00
Blaise Tine 3e1fe66d9e minor update 2020-11-16 08:25:45 -08:00
Blaise Tine 2234735cfb constant integration updates 2020-11-16 03:55:55 -08:00
Blaise Tine 77bca2deca constant integration updates 2020-11-16 02:39:53 -08:00
Blaise Tine 18ff70bc7f constant integration updates 2020-11-16 01:23:03 -08:00
Blaise Tine a1fcdd467a reset networks optimization 2020-11-16 01:12:02 -08:00
Blaise Tine 1bc4b8e7a8 constant integration updates, cache bank incoming_fill optimization 2020-11-15 23:01:24 -08:00