wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
1,718 Commits 9 Branches 0 Tags
d2f9c66840400c08287c0fb89ec676e6cdbf927c
Commit Graph
115 Commits
Author SHA1 Message Date
Blaise Tine 86aabbbf5d minor update 2021-06-28 08:00:29 -07:00
Blaise Tine 1ea738ed26 lkg build 2021-06-25 16:28:10 -07:00
Blaise Tine 2372067817 minor update 2021-06-22 09:30:36 -07:00
Blaise Tine c331da5ff7 adding fast DPI implemntation of imul and idiv 2021-06-22 09:02:41 -07:00
Blaise Tine 6213b1a910 vortex runtime console out implementation 2021-06-15 04:01:44 -04:00
Blaise Tine a315d0087d opae_sim buffer index allocation bug fix 2021-06-11 15:20:02 -07:00
Blaise Tine 3cc1190cd7 CSRs I/O refactoring 2021-06-11 03:08:07 -07:00
Blaise Tine df7d91d690 more testing 2021-05-26 15:29:39 -07:00
Blaise Tine b3e54e66f8 fixed compiler warnings 2021-05-23 10:54:06 -07:00
Blaise Tine bde6a69ea0 adding support for multi-banks memory bus 2021-05-04 07:32:03 -07:00
Blaise Tine d504adb236 afu mem controller refactoring 2021-05-01 08:39:52 -07:00
Blaise Tine 95f057bc2e fpga build refactoring 2021-04-29 06:17:28 -07:00
Blaise Tine 2216a3059d minor update 2021-04-27 05:52:01 -04:00
Blaise Tine 64848788a1 minor update 2021-04-26 20:34:28 -07:00
Blaise Tine 8543e3a8bf code refactoring 2021-04-26 02:34:21 -07:00
Blaise Tine 8410c49f53 code refactoring: DRAM => MEM renaming 2021-04-26 00:58:48 -07:00
Blaise Tine cad21a4b92 minor update 2021-04-24 01:17:38 -04:00
Blaise Tine 4cb98a25a7 enabling 128-bit dram bus 2021-04-24 00:31:27 -04:00
Blaise Tine 3a266fc792 adding compiler tests to regression suite 2021-03-09 05:01:56 -08:00
Blaise Tine ad11bdfc87 fix warnings 2021-03-09 04:58:00 -08:00
Blaise Tine c0abd6ef3f Aligned memory allocation workaround for PACE clusters 2021-03-09 03:25:45 -08:00
Blaise Tine 66ea340d05 Fix RAM memory deallocation 2021-03-09 01:52:56 -08:00
Blaise Tine 907e6868cd simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite 2021-03-08 23:58:33 -08:00
Blaise Tine 062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
Blaise Tine 41f09ffb55 minor update - allow independent driver cleanup 2021-02-28 18:19:26 -08:00
Blaise Tine a9f82bceae updating kernels with 32-cores support 2021-01-25 10:33:42 -05:00
Blaise Tine 5419859281 fcvt fix 2021-01-25 02:22:00 -08:00
Blaise Tine 7ae936c25f minor updates 2021-01-14 23:06:03 -08:00
Blaise Tine fe64c47f60 ccip write fix 2021-01-14 22:49:06 -08:00
Blaise Tine 146c285aa0 minor update 2021-01-06 19:59:04 -08:00
Blaise Tine 2b8435471a speeding up simulation using dedicated full dpi-based FPU core 2021-01-06 18:44:06 -08:00
Blaise Tine 39bff921be cache bug fixes 2021-01-05 05:04:49 -08:00
Blaise Tine 762b8e2e3e fixed cache mshr critical path 2021-01-04 12:49:40 -05:00
Blaise Tine 4bc3b537bd fixed reset fan-out 2021-01-03 20:06:36 -08:00
Blaise Tine 4815ab099c using single-port block ram for cache tags, restoring core reset signal 2021-01-02 19:53:41 -08:00
Blaise Tine e4a00dd0d9 fixed loader script stack setup 2020-12-31 22:37:20 -05:00
Blaise Tine 703a861fe9 added support for write-through cache, removed cache snooping support 2020-12-23 23:51:02 -08:00
Blaise Tine 4bbd7bf408 performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies, 2020-12-19 02:45:06 -08:00
Blaise Tine 29cd2f5dff fixed register file initialization to zero synthesis inference 2020-12-10 00:27:56 -08:00
Blaise Tine 707ba3760f minor update 2020-12-08 21:37:53 -08:00
Blaise Tine d5438fd591 merging perf counters 2020-12-08 21:02:39 -08:00
Blaise Tine 14baec86d5 moved apae sources into rtl/afu 2020-12-08 04:59:11 -08:00
Blaise Tine d5fa82f5e4 cache req datapath optimizations 2020-12-08 02:58:08 -08:00
Blaise Tine d68b32cd60 minor update 2020-12-06 22:40:27 -08:00
Blaise Tine b7a724410b update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache) 2020-12-03 07:30:19 -08:00
Blaise Tine b85391389b rename MSRQ to MSHR 2020-11-28 17:32:00 -05:00
Blaise Tine 00d7473268 build warnings clean 2020-11-28 14:59:13 -05:00
Blaise Tine 461be0880d fixed FPU-CSR data dependence 2020-11-25 09:05:38 -08:00
Blaise Tine c04d385641 minor update 2020-11-23 20:12:04 -08:00
Blaise Tine 664ce28426 minor update 2020-11-23 12:21:39 -08:00