5 Commits

Author	SHA1	Message	Date
felsabbagh3	469334f23e	MULTICORE WITH L2 WORKING	2020-03-09 01:17:11 -07:00
Blaise Tine	369c2c625c	synthesis fixes	2020-03-05 06:58:51 -05:00
wgulian3	3e68c8bcf5	verilator does not support delayed assignment in a loop	2020-02-18 13:38:17 -05:00
wgulian3	e76d05f7ce	Fix issues quartus synthesis issues	2020-02-18 13:24:18 -05:00
felsabbagh3	be66e51613	Added CSRs, some Load unit tests are failing	2020-02-17 22:22:27 -08:00