Blaise Tine
b0b7cd2b1e
minor updates
2024-02-03 19:09:53 -08:00
Blaise Tine
38b92ad592
- using SV_DPI defines to disable DPI in synthesis-based simulations
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- fixed Intel ASE run script: run_ase.sh
2024-01-28 00:22:21 -08:00
Blaise Tine
031d24e695
minor updates
2023-12-30 00:52:44 -08:00
Blaise Tine
c7a81d1493
adding sockets support to simx and cache subsystem refactoring
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minor update
minor update
minor updates
2023-12-20 15:16:12 -08:00
Blaise Tine
c6845a4c8d
profiling timing optimization
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minor update
minor update
minor update
2023-12-18 04:43:10 -08:00
Blaise Tine
6c7ac35054
profiling optimizations
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minor updates
2023-12-18 04:43:00 -08:00
Blaise Tine
d65cc61df5
minor update
2023-11-16 12:00:37 -08:00
Blaise Tine
547d916ae2
minor update
2023-11-15 13:00:06 -08:00
Blaise Tine
c1e168fdbe
Vortex 2.0 changes:
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+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
minor update
minor update
minor update
minor update
minor update
minor update
cleanup
cleanup
cache bindings and memory perf refactory
minor update
minor update
hw unit tests fixes
minor update
minor update
minor update
minor update
minor update
minor udpate
minor update
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor updates
minor updates
minor update
minor update
2023-11-10 02:47:05 -08:00
Santosh Srivatsan
836c777680
XLEN parameterization for simx
2022-02-03 15:19:31 -05:00
Santosh Srivatsan
91c22a2592
Fixed some riscv-tests
2022-01-22 12:54:10 -05:00
Santosh Srivatsan
d762d401cd
Added 64-bit linker script
2022-01-11 17:22:16 -05:00
Santosh Srivatsan
e82d5fe48f
Removed all comments labelled \'simx64\'
2021-12-13 19:52:13 -05:00
Santosh Srivatsan
5edb9098ce
Merge branch 'simx64'
2021-12-10 21:48:29 -05:00
Santosh Raghav Srivatsan
f0dc04ad04
Added tests to commit. 64 bit simx still not working
2021-12-01 02:44:14 -05:00
Blaise Tine
4477cbeed1
blackbox caching fix
2021-11-30 15:36:59 -05:00
Blaise Tine
41d7e6c63a
cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
2021-11-30 07:08:15 -05:00
Blaise Tine
18762dffce
fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id,
2021-11-24 00:00:17 -05:00
Blaise Tine
9656779d48
minor update
2021-11-14 04:45:06 -05:00
Blaise Tine
58a2140b92
merge update
2021-10-15 19:58:13 -07:00
Blaise Tine
e380ded5e1
Merge branch 'master' into graphics
2021-10-15 19:32:11 -07:00
Blaise Tine
9f34b2944c
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
Blaise Tine
4e8293c3e3
cache bank pipeline optimization
2021-09-14 02:09:35 -07:00
Blaise Tine
90b50277d0
cache multi-porting fixes + optimization
2021-08-29 18:33:49 -07:00
Blaise Tine
6674e8c44a
cache bank area optimization + multi-porting fix for l2/l3 caches
2021-08-28 21:34:06 -07:00
Blaise Tine
6caf674163
minor update
2021-08-16 04:47:08 -07:00
Blaise Tine
0debdd3fe7
minor update
2021-08-08 02:59:30 -07:00
Blaise Tine
e4d9fd8a00
thread mask redesign
2021-08-05 17:32:58 -07:00
Blaise Tine
7b921387bc
Merge branch 'master' into graphics
2021-08-02 23:57:53 -07:00
Blaise Tine
91d4419fae
new regression tests
2021-08-02 16:05:33 -07:00
Blaise Tine
bb1ceffadd
rebase master update
2021-07-30 21:03:14 -07:00
Blaise Tine
d2aa228a34
cache area optimization + IPC boost from 4.24 => 4.42
2021-07-26 21:24:27 -07:00
Blaise Tine
e0487e4555
minor reset delay fix
2021-07-16 21:31:46 -07:00
Blaise Tine
53b3d42908
cache's core response queue size control
2021-07-16 13:09:29 -07:00
Blaise Tine
2372067817
minor update
2021-06-22 09:30:36 -07:00
Blaise Tine
6213b1a910
vortex runtime console out implementation
2021-06-15 04:01:44 -04:00
Blaise Tine
76c4909ae9
minor update
2021-06-12 02:22:01 -04:00
Blaise Tine
3cc1190cd7
CSRs I/O refactoring
2021-06-11 03:08:07 -07:00
Blaise Tine
3071fb7a29
adding support for non-cacheable memory addressing
2021-06-06 13:35:55 -07:00
Blaise Tine
64848788a1
minor update
2021-04-26 20:34:28 -07:00
Blaise Tine
8543e3a8bf
code refactoring
2021-04-26 02:34:21 -07:00
Blaise Tine
8410c49f53
code refactoring: DRAM => MEM renaming
2021-04-26 00:58:48 -07:00
Blaise Tine
cad21a4b92
minor update
2021-04-24 01:17:38 -04:00
Blaise Tine
4cb98a25a7
enabling 128-bit dram bus
2021-04-24 00:31:27 -04:00
Blaise Tine
3f5fd6d394
using shiftreg-based skid buffers
2021-02-28 02:20:09 -08:00
Blaise Tine
700f9eea19
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
Blaise Tine
7560202f8b
cache bank refactoring - removing unecessary core response fifo & restoring single port data access
2021-02-21 21:47:46 -08:00
Blaise Tine
3c37db877a
cache specialization for in-order DRAM reponses
2021-02-13 20:23:29 -08:00
Blaise Tine
073964fdf7
minor update
2021-02-12 08:52:06 -08:00
Blaise Tine
665b97b810
multi-ported cache support for streaming
2021-02-08 16:13:32 -08:00
