Blaise Tine
|
5419859281
|
fcvt fix
|
2021-01-25 02:22:00 -08:00 |
|
Blaise Tine
|
8775f63ec4
|
lkg build rollout with 16cores optimization on arria10
|
2021-01-24 16:49:22 -08:00 |
|
Blaise Tine
|
74a687e395
|
minor updates
|
2021-01-18 05:43:30 -08:00 |
|
Blaise Tine
|
a7f6b9fffc
|
minor updates
|
2021-01-17 18:18:05 -08:00 |
|
Blaise Tine
|
8b42393189
|
minor updates
|
2021-01-17 17:33:41 -08:00 |
|
Blaise Tine
|
a046bd7a73
|
cache pipeline optimization
|
2021-01-17 17:19:52 -08:00 |
|
Blaise Tine
|
ed216ab39d
|
minor updates
|
2021-01-17 13:58:43 -08:00 |
|
Blaise Tine
|
a69ba5ad7b
|
cache flush support
|
2021-01-17 05:50:29 -08:00 |
|
Blaise Tine
|
d4e7b28be8
|
cache refactoring
|
2021-01-17 00:18:56 -08:00 |
|
Blaise Tine
|
4f26228d50
|
minor updates
|
2021-01-16 05:33:28 -08:00 |
|
Blaise Tine
|
fcbf57b66a
|
specialized shared memory module
|
2021-01-16 04:41:58 -08:00 |
|
Blaise Tine
|
f146178c2d
|
minor updates
|
2021-01-13 15:52:03 -08:00 |
|
Blaise Tine
|
0e1650e1c2
|
bank deadlock fix
|
2021-01-13 15:51:42 -08:00 |
|
Blaise Tine
|
79cc4d98e6
|
bank deadlock fix
|
2021-01-13 13:06:07 -08:00 |
|
Blaise Tine
|
464c4f4bd8
|
minor updates
|
2021-01-12 20:16:59 -08:00 |
|
Blaise Tine
|
e770824d47
|
fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance
|
2021-01-10 20:26:15 -08:00 |
|
Blaise Tine
|
06945533cf
|
fixed l2/l3 caches related bugs
|
2021-01-09 16:32:55 -08:00 |
|
Blaise Tine
|
2058718f0f
|
minor updates
|
2021-01-06 07:18:14 -08:00 |
|
Blaise Tine
|
31ff70fd4e
|
minor updates
|
2021-01-05 15:03:41 -08:00 |
|
Blaise Tine
|
846a4036d3
|
minor update
|
2021-01-05 05:46:20 -08:00 |
|
Blaise Tine
|
39bff921be
|
cache bug fixes
|
2021-01-05 05:04:49 -08:00 |
|
Blaise Tine
|
762b8e2e3e
|
fixed cache mshr critical path
|
2021-01-04 12:49:40 -05:00 |
|
Blaise Tine
|
4d55118545
|
cache pipeline optimization - moved tag access to stage0
|
2021-01-03 23:10:41 -05:00 |
|
Blaise Tine
|
9cef1aae04
|
cache fill response address is the mshr's top address, no need to store it
|
2021-01-03 00:57:24 -05:00 |
|
Blaise Tine
|
a825941f51
|
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
|
2021-01-02 16:06:09 -05:00 |
|
Blaise Tine
|
2d69ca5d67
|
scratchpad optimization for stack access using custom bank offset aligned to stack size
|
2021-01-02 16:00:00 -05:00 |
|
Blaise Tine
|
93c36273fa
|
minor update
|
2021-01-01 20:24:18 -08:00 |
|
Blaise Tine
|
b2cfde5d6d
|
enabling shared memory back
|
2020-12-31 19:19:14 -08:00 |
|
Blaise Tine
|
abe32ed553
|
cache optimization - moved read requests to stage1 and eliminating stage3
|
2020-12-31 07:40:58 -08:00 |
|
Blaise Tine
|
d44144f72f
|
FPU float<->int conversion optimization
|
2020-12-29 15:37:45 -08:00 |
|
Blaise Tine
|
703a861fe9
|
added support for write-through cache, removed cache snooping support
|
2020-12-23 23:51:02 -08:00 |
|
Blaise Tine
|
d956e268b9
|
adding new performance counters (banks utilization and DRAM bus utilization)
|
2020-12-22 12:33:45 -08:00 |
|
Blaise Tine
|
4b7d871d62
|
allowing partial cache request submissions, io bus support broken
|
2020-12-21 03:53:13 -08:00 |
|
Blaise Tine
|
4bbd7bf408
|
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
|
2020-12-19 02:45:06 -08:00 |
|
Blaise Tine
|
d5438fd591
|
merging perf counters
|
2020-12-08 21:02:39 -08:00 |
|
Blaise Tine
|
d5fa82f5e4
|
cache req datapath optimizations
|
2020-12-08 02:58:08 -08:00 |
|
Xandy Liu
|
1595ff08e2
|
PERF pipeline stalls and cache
|
2020-12-08 01:14:41 -05:00 |
|
Blaise Tine
|
268ad15098
|
minor update
|
2020-12-06 22:55:17 -08:00 |
|
Blaise Tine
|
d68b32cd60
|
minor update
|
2020-12-06 22:40:27 -08:00 |
|
Blaise Tine
|
13a5370254
|
register file refactoring
|
2020-12-05 01:40:50 -08:00 |
|
Blaise Tine
|
fb60d0af87
|
decoupled load/store commits
|
2020-12-03 15:08:48 -08:00 |
|
Blaise Tine
|
f3b1069ce8
|
adding stream arbiter
|
2020-12-03 06:40:23 -08:00 |
|
Blaise Tine
|
f68af3bb84
|
using mshr pending request size
|
2020-12-01 00:54:25 -08:00 |
|
Blaise Tine
|
97739e9dcf
|
RAM blocks inference fixes
|
2020-11-30 14:02:47 -08:00 |
|
Blaise Tine
|
5758ef9ebf
|
generic_register reset network optimization
|
2020-11-29 18:41:36 -08:00 |
|
Blaise Tine
|
def6a35693
|
shared memory optimization
|
2020-11-29 15:04:31 -08:00 |
|
Blaise Tine
|
b85391389b
|
rename MSRQ to MSHR
|
2020-11-28 17:32:00 -05:00 |
|
Blaise Tine
|
7a7011d5c6
|
minor update (trace log)
|
2020-11-23 14:29:35 -05:00 |
|
Blaise Tine
|
1795980a52
|
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
|
2020-11-21 09:47:56 -08:00 |
|
Blaise Tine
|
34b650be94
|
fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug
|
2020-11-17 00:27:24 -08:00 |
|