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aeeb3ca616b27ff8bc9e14f5b4676cd06787c10a
Commit Graph
20 Commits
Author SHA1 Message Date
Blaise Tine 0d91f8771e Workaround fix for Verilator bug with array indexing 2021-09-07 23:28:54 -07:00
Blaise Tine af1cecae07 stream arbiter update 2021-09-06 23:38:20 -07:00
Blaise Tine b52ace5142 area optimization bundle 2021-09-05 23:35:44 -07:00
Blaise Tine 74a45e2772 stream arbiter optimization (using indexing instead of onehot mux) 2021-08-26 09:52:13 -07:00
Blaise Tine f12be56d7c fixed Verilator warnings 2021-08-13 05:52:43 -04:00
Blaise Tine 3d19588e57 bus arbiters refactoring 2021-07-30 16:00:09 -07:00
Blaise Tine ea1e0f201e OUTPUT_REG refactoring 2021-07-23 06:58:37 -07:00
Blaise Tine 22cf698e69 minor update 2021-07-13 05:25:44 -07:00
Blaise Tine 10e9ee124b using onehot multiplexer to reduce critical path 2021-07-08 00:26:59 -07:00
Blaise Tine dc34c5c5bd minor update 2021-07-03 04:47:19 -07:00
Blaise Tine 93fee18d59 minor update 2021-07-01 02:59:44 -07:00
Blaise Tine adf033b0aa non-cacheable memory address critical paths optimizations 2021-06-10 12:47:18 -07:00
Blaise Tine 3f5fd6d394 using shiftreg-based skid buffers 2021-02-28 02:20:09 -08:00
Blaise Tine 073964fdf7 minor update 2021-02-12 08:52:06 -08:00
Blaise Tine 8775f63ec4 lkg build rollout with 16cores optimization on arria10 2021-01-24 16:49:22 -08:00
Blaise Tine 4bbd7bf408 performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies, 2020-12-19 02:45:06 -08:00
Blaise Tine d5fa82f5e4 cache req datapath optimizations 2020-12-08 02:58:08 -08:00
Blaise Tine 13a5370254 register file refactoring 2020-12-05 01:40:50 -08:00
Blaise Tine c3ec4c9e90 minor update 2020-12-03 09:30:59 -08:00
Blaise Tine f3b1069ce8 adding stream arbiter 2020-12-03 06:40:23 -08:00