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Author SHA1 Message Date
Blaise Tine b7e892ee16 rtl refactoring 2020-05-05 10:46:48 -04:00
Blaise Tine f142afac80 rtl refactoring 2020-05-04 20:12:05 -04:00
Blaise Tine 69f607b73e rtl refactoring 2020-05-03 17:10:02 -04:00
Blaise Tine a1dc90b951 rtl cache refactory 2020-04-30 17:12:18 -04:00
Blaise Tine 814ac50d12 RTL code refactoring 2020-04-23 14:24:53 -04:00
Blaise Tine 2846809823 RTL code refactoring 2020-04-23 14:12:08 -04:00
Blaise Tine f79067fb52 RTL code refactoring 2020-04-23 13:55:54 -04:00
Blaise Tine 00a5122fd4 RTL code refactoring 2020-04-23 13:49:45 -04:00
Blaise Tine 3cf1a5074b RTL code refactoring 2020-04-23 12:50:02 -04:00
Blaise Tine 28d054e295 RTL code refactoring 2020-04-23 12:38:44 -04:00
Blaise Tine f0e257bc8e minor update 2020-04-23 09:09:01 -04:00
Tine, BlaiseandGitHub Enterprise 016a4fdb60 Delete basic 2020-04-23 06:24:00 -04:00
Tine, BlaiseandGitHub Enterprise 99bcc91a70 Delete demo 2020-04-23 06:23:47 -04:00
Blaise Tine 77a52ea20b optimized opae cci to dev memcpy using double buffering and request window to work around unordered read requests 2020-04-23 01:30:45 -07:00
Blaise Tine 3e64cb4380 minor update 2020-04-21 22:24:05 -04:00
Blaise Tine e95af111a5 update 2020-04-21 17:52:27 -04:00
Blaise Tine 38f73af627 update 2020-04-21 17:50:42 -04:00
Blaise Tine 24c81c4a3a merge 2020-04-21 12:32:46 -07:00
Blaise Tine f53256f854 quartus projects 2020-04-21 12:28:37 -07:00
Blaise Tine 43d8922f64 minor update 2020-04-21 15:21:59 -04:00
Blaise Tine 5798cf6e15 RTL refactoring 2020-04-21 07:13:56 -07:00
Blaise Tine b6ce2dd3b8 opae build fix 2020-04-21 02:08:20 -07:00
Blaise Tine cb0afd3eec fix quartus build 2020-04-21 00:55:18 -07:00
Blaise Tine d6255f0445 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis 2020-04-21 03:20:18 -04:00
Blaise Tine d85c0af5d6 remove tab spaces 2020-04-21 03:19:47 -04:00
Blaise Tine 07d308d2ce update 2020-04-21 02:41:37 -04:00
Blaise Tine 43a8bf4326 RTL code refactoring 2020-04-21 01:52:12 -04:00
Blaise Tine 20ae78f434 fix simX build 2020-04-21 01:31:32 -04:00
Blaise Tine ba4e736782 RTL code refactoring 2020-04-21 01:03:37 -04:00
Blaise Tine cfa8626bf7 RTL code refactoring 2020-04-20 23:44:30 -04:00
Blaise Tine 786817d601 opae build fix 2020-04-20 19:53:47 -07:00
Blaise Tine d79e36912f fix opae build 2020-04-20 12:51:42 -07:00
Blaise Tine 3cbecfcef0 opae build fix 2020-04-20 12:32:01 -07:00
Blaise Tine f835fabbe3 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis 2020-04-20 15:07:49 -04:00
Blaise Tine b76f8696bd removing *.vh file for opae build 2020-04-20 15:07:27 -04:00
Blaise Tine 91207a0fcb opae update 2020-04-20 12:06:47 -07:00
Blaise Tine 8e7046a388 RTL code refactoring 2020-04-20 14:05:08 -04:00
Blaise Tine 1a2823da0d RTL code refactoring 2020-04-20 13:52:24 -04:00
Blaise Tine 94e4f056db RTL code refactoring 2020-04-20 13:10:56 -04:00
Blaise Tine a0e15af0dc RTL code refactoring 2020-04-20 13:01:42 -04:00
Blaise Tine e8a4923eb4 RTL code refactoring 2020-04-20 12:09:30 -04:00
Blaise Tine e8072bab77 RTL code refactoring 2020-04-20 11:20:41 -04:00
Blaise Tine 45990e391f RTL code refactoring 2020-04-20 10:21:06 -04:00
Blaise Tine 0c81a3ae19 RTL code refactoring 2020-04-20 08:01:46 -04:00
Blaise Tine 62c1c3fdbb RTL code refactoring 2020-04-20 07:24:20 -04:00
Blaise Tine 58850a2fe8 RTL code refactoring 2020-04-20 06:59:13 -04:00
Blaise Tine 07135263f5 RTL code refactoring 2020-04-20 06:47:24 -04:00
Blaise Tine 5671b08a5e merge 2020-04-20 06:06:54 -04:00
felsabbagh3 5e570d95d8 Fixed two variabled driving the dram_delay signal 2020-04-20 00:33:24 -07:00
Blaise Tine e9dfa828fe RTL code refactoring 2020-04-19 09:24:04 -04:00